ASIC/RTL Design Engineer - Senior (US)

Lead the design and development of next-generation, high-performance System-on-a-Chip (SoC) projects from architecture to implementation. Convert micro-architectural specifications into high-quality, synthesizable RTL using

SystemVerilog/Verilog . Integrate complex third-party and internal IPs, including

ARM cores

and high-speed interfaces like

PCIe

and

DDR . Run, analyze, and debug results from front-end quality checks, including Lint,

Clock Domain Crossing (CDC) , and

Reset Domain Crossing (RDC) . Collaborate with verification and physical design teams to ensure successful synthesis, timing closure, and silicon bring-up. Utilize your scripting skills in

TCL

and

Python

to automate tasks within the front-end design flow.

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