Altera
Overview
Join to apply for the
Product Development Architect
role at
Altera . Altera is searching for a
Product Development Architect
to join our Manufacturing Content Development Engineering Group. Base pay range
$159,700.00/yr - $231,200.00/yr Additional compensation
Annual Bonus and Sign-on bonus Job details
Salary Range : The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance. Job Type : Regular Primary Location : San Jose, California, United States Responsibilities
Develop and implement DFT strategies for FPGAs, including scan insertion, BIST (Built-In Self-Test), and test compression techniques. Collaborate with RTL design and verification teams to ensure testability features are embedded efficiently. Define and implement test plans, patterns, and fault models to ensure optimal test coverage and yield. Develop and maintain ATPG (Automatic Test Pattern Generation), MBIST, and other manufacturing test content flows and scripts. Perform pre-silicon test pattern simulation and validation to ensure test effectiveness prior to tape-out. Analyze test results, debug silicon failures, and provide root cause analysis. Work with manufacturing and test teams to optimize test time, cost, and quality. Analyze early customer returns with emphasis on driving test hole closure activities. Drive test time reduction through analysis of fallout data versus test time for various IPs to balance and drive overall product cost optimizations. Mentor junior engineers and lead DFT efforts across multiple projects. Stay updated with industry trends and emerging DFT/test technologies. Qualifications
Minimum Required Qualifications: Bachelor’s Degree in Electrical Engineering, or equivalent (or other related engineering degree) and 10+ years of experience. Experience with DFT methodologies: scan chains, BIST, boundary scan, test compression, and JTAG. Experience with ATPG tools (e.g., Tessent, FastScan, Synopsys TetraMAX). Experience with RTL design, synthesis, and verification flows. Scripting experience in Python, Perl, TCL, or similar. Experience with fault grading, test coverage analysis, and test yield enhancement. Experience with semiconductor manufacturing test processes. Preferred Qualifications: Master's Degree in Electrical Engineering, or equivalent (or related engineering degree). Experience with machine learning applied to test optimization. Experience with Automated Test Equipment (ATE) and its operation for silicon testing. Seniority and employment
Seniority level : Mid-Senior level Employment type : Full-time Industry
Semiconductor Manufacturing Posting and notices
Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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Join to apply for the
Product Development Architect
role at
Altera . Altera is searching for a
Product Development Architect
to join our Manufacturing Content Development Engineering Group. Base pay range
$159,700.00/yr - $231,200.00/yr Additional compensation
Annual Bonus and Sign-on bonus Job details
Salary Range : The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance. Job Type : Regular Primary Location : San Jose, California, United States Responsibilities
Develop and implement DFT strategies for FPGAs, including scan insertion, BIST (Built-In Self-Test), and test compression techniques. Collaborate with RTL design and verification teams to ensure testability features are embedded efficiently. Define and implement test plans, patterns, and fault models to ensure optimal test coverage and yield. Develop and maintain ATPG (Automatic Test Pattern Generation), MBIST, and other manufacturing test content flows and scripts. Perform pre-silicon test pattern simulation and validation to ensure test effectiveness prior to tape-out. Analyze test results, debug silicon failures, and provide root cause analysis. Work with manufacturing and test teams to optimize test time, cost, and quality. Analyze early customer returns with emphasis on driving test hole closure activities. Drive test time reduction through analysis of fallout data versus test time for various IPs to balance and drive overall product cost optimizations. Mentor junior engineers and lead DFT efforts across multiple projects. Stay updated with industry trends and emerging DFT/test technologies. Qualifications
Minimum Required Qualifications: Bachelor’s Degree in Electrical Engineering, or equivalent (or other related engineering degree) and 10+ years of experience. Experience with DFT methodologies: scan chains, BIST, boundary scan, test compression, and JTAG. Experience with ATPG tools (e.g., Tessent, FastScan, Synopsys TetraMAX). Experience with RTL design, synthesis, and verification flows. Scripting experience in Python, Perl, TCL, or similar. Experience with fault grading, test coverage analysis, and test yield enhancement. Experience with semiconductor manufacturing test processes. Preferred Qualifications: Master's Degree in Electrical Engineering, or equivalent (or related engineering degree). Experience with machine learning applied to test optimization. Experience with Automated Test Equipment (ATE) and its operation for silicon testing. Seniority and employment
Seniority level : Mid-Senior level Employment type : Full-time Industry
Semiconductor Manufacturing Posting and notices
Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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