Altera
Senior Director, FPGA Compiler Organization
Altera, San Jose, California, United States, 95199
Altera
.Senior Director, FPGA Compiler Organization page is loaded## Senior Director, FPGA Compiler Organizationlocations:
San Jose, California, United Statestime type:
Full timeposted on:
Posted Yesterdayjob requisition id:
R01208# **Job Details:**### ## **Job Description:**Altera Corporation is seeking a visionary and accomplished senior leader to head our FPGA Compiler Organization. This leader will drive innovation and execution in the development of advanced compiler technologies and algorithms, with a focus on synthesis, physical synthesis, place and route, and timing analysis for FPGA platforms. The ideal candidate is a recognized leader in EDA software, brings a passion for leveraging AI to optimize compiler performance and usability, and has a proven track record of building and leading high-performing teams.**Key Responsibilities:*** Provide strategic and operational leadership for the FPGA Compiler Organization, overseeing roadmap development, architecture, execution, and delivery of world-class EDA tools and solutions.* Drive research and development in synthesis, physical synthesis, place and route, and timing analysis to enable next-generation FPGA capabilities.* Champion the adoption of AI/ML techniques to enhance compiler optimization, automation, and ease of use within the EDA/FPGA toolchain.* Collaborate closely with senior technologists to shape the technical direction and turn strategic directions into actionable initiatives with execution excellence.* Build, mentor, and inspire a diverse, multidisciplinary team of engineers and researchers, fostering a culture of innovation, technical excellence, and accountability.* Engage with internal and external stakeholders, including product management, hardware engineering, and customers, to align compiler capabilities with business goals and market needs.* Represent Altera in industry forums, conferences, and customer engagements as a thought leader in EDA and FPGA compilation.* Set and manage budgets, resource allocation, and organizational structure to scale the team and deliver on aggressive timelines.**Salary Range**The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.$221.5k- $327.0k USD#LI-ALTERA### ## **Qualifications:****Qualifications:*** 20+ years leading multi-site EDA software teams, with proven delivery of production-quality EDA design implementation compilers and analysis tools.* Strong expertise in logic synthesis, physical synthesis, placement, routing, timing closure, and power optimization.* Demonstrated experience applying AI/ML to EDA compiler optimization problems.* Deep FPGA/ASIC compilation knowledge (Quartus, Vivado, Synplify, Fusion Compiler, Innovus, or equivalent).* Proven track record to lead a global organization, managing execution, and delivering results for QoR and productivity improvements.* Skilled at defining and executing compiler roadmaps aligned with device architecture, that is aligned to customer and market needs.* Proven ability to build, mentor, and retain high-performing engineering teams.* Excellent communication skills with strong track record of cross-functional collaboration with software, hardware, modeling, and infrastructure teams.* MS/PhD in Computer Science, Electrical Engineering, or related field.### ## **Job Type:**Regular### ## **Shift:**Shift 1 (United States of America)### ## **Primary Location:**San Jose, California, United States### ## **Additional Locations:**### ## **Posting Statement:**All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. #J-18808-Ljbffr
.Senior Director, FPGA Compiler Organization page is loaded## Senior Director, FPGA Compiler Organizationlocations:
San Jose, California, United Statestime type:
Full timeposted on:
Posted Yesterdayjob requisition id:
R01208# **Job Details:**### ## **Job Description:**Altera Corporation is seeking a visionary and accomplished senior leader to head our FPGA Compiler Organization. This leader will drive innovation and execution in the development of advanced compiler technologies and algorithms, with a focus on synthesis, physical synthesis, place and route, and timing analysis for FPGA platforms. The ideal candidate is a recognized leader in EDA software, brings a passion for leveraging AI to optimize compiler performance and usability, and has a proven track record of building and leading high-performing teams.**Key Responsibilities:*** Provide strategic and operational leadership for the FPGA Compiler Organization, overseeing roadmap development, architecture, execution, and delivery of world-class EDA tools and solutions.* Drive research and development in synthesis, physical synthesis, place and route, and timing analysis to enable next-generation FPGA capabilities.* Champion the adoption of AI/ML techniques to enhance compiler optimization, automation, and ease of use within the EDA/FPGA toolchain.* Collaborate closely with senior technologists to shape the technical direction and turn strategic directions into actionable initiatives with execution excellence.* Build, mentor, and inspire a diverse, multidisciplinary team of engineers and researchers, fostering a culture of innovation, technical excellence, and accountability.* Engage with internal and external stakeholders, including product management, hardware engineering, and customers, to align compiler capabilities with business goals and market needs.* Represent Altera in industry forums, conferences, and customer engagements as a thought leader in EDA and FPGA compilation.* Set and manage budgets, resource allocation, and organizational structure to scale the team and deliver on aggressive timelines.**Salary Range**The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.$221.5k- $327.0k USD#LI-ALTERA### ## **Qualifications:****Qualifications:*** 20+ years leading multi-site EDA software teams, with proven delivery of production-quality EDA design implementation compilers and analysis tools.* Strong expertise in logic synthesis, physical synthesis, placement, routing, timing closure, and power optimization.* Demonstrated experience applying AI/ML to EDA compiler optimization problems.* Deep FPGA/ASIC compilation knowledge (Quartus, Vivado, Synplify, Fusion Compiler, Innovus, or equivalent).* Proven track record to lead a global organization, managing execution, and delivering results for QoR and productivity improvements.* Skilled at defining and executing compiler roadmaps aligned with device architecture, that is aligned to customer and market needs.* Proven ability to build, mentor, and retain high-performing engineering teams.* Excellent communication skills with strong track record of cross-functional collaboration with software, hardware, modeling, and infrastructure teams.* MS/PhD in Computer Science, Electrical Engineering, or related field.### ## **Job Type:**Regular### ## **Shift:**Shift 1 (United States of America)### ## **Primary Location:**San Jose, California, United States### ## **Additional Locations:**### ## **Posting Statement:**All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. #J-18808-Ljbffr