AMD
Base pay range
$159,840.00/yr - $239,760.00/yr Overview
AMD provides a pay range based on skills and experience; your actual pay will be discussed with your recruiter. The Role
Our NTSG - Network Technology Solutions Group team working with the AMD Pensando DPU product is a leading provider of innovative Data Center infrastructure, AI NIC (GPU-to-GPU communication), and networking technologies. We are seeking a dynamic, energetic candidate to join the AMD Pensando DPU Group. We are seeking a highly motivated and experienced ASIC Implementation Engineer to lead the implementation of complex ASIC designs, from synthesis to tape-out, working closely with architects, designers, and physical design teams. The Person
You have a passion for modern technology, complex processor architecture, and digital design. You are a team player with excellent communication skills, a proactive approach, and experience collaborating with engineers in different sites/time zones. You have strong analytical and problem-solving skills and are eager to learn and tackle challenging problems. Key Responsibilities
Run Logic/Physical synthesis using advanced techniques to generate netlists with optimized power, performance, and area. Perform logic equivalency checks for blocks/chip and analyze/debug the results. Conduct flat and hierarchical clock domain crossing analysis and collaborate with designers to address complex clock domain crossings. Execute flat and hierarchical reset domain crossing checks and understand reset architecture with designers. Perform RTL Lint and collaborate with designers to create waivers. Create timing constraints for synthesis. Develop automation scripts and methodologies for Front-end tools including LINT, CDC, RDC, SYN, LEC. Preferred Qualifications
Strong experience in Synthesis. Experience with LINT, Clock domain crossing, and reset domain crossing signoff. Proficiency in Logic equivalency checks. Knowledge of front-end ASIC flows. Experience in communicating across functional internal teams and vendors. Scripting and programming experience using Perl, TCL, Python, Cshell, and Make. Experience with SOC design integration and Front-end implementation. Knowledge of Timing/physical libraries and memories. Familiarity with Design Compiler, Fusion Compiler, Spyglass, Zero-in, Primetime, Formality, and Conformal LEC. Academic Credentials
BSEE or equivalent. MSEE preferred Location
Santa Clara, CA Benefits and Equal Opportunity
AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
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$159,840.00/yr - $239,760.00/yr Overview
AMD provides a pay range based on skills and experience; your actual pay will be discussed with your recruiter. The Role
Our NTSG - Network Technology Solutions Group team working with the AMD Pensando DPU product is a leading provider of innovative Data Center infrastructure, AI NIC (GPU-to-GPU communication), and networking technologies. We are seeking a dynamic, energetic candidate to join the AMD Pensando DPU Group. We are seeking a highly motivated and experienced ASIC Implementation Engineer to lead the implementation of complex ASIC designs, from synthesis to tape-out, working closely with architects, designers, and physical design teams. The Person
You have a passion for modern technology, complex processor architecture, and digital design. You are a team player with excellent communication skills, a proactive approach, and experience collaborating with engineers in different sites/time zones. You have strong analytical and problem-solving skills and are eager to learn and tackle challenging problems. Key Responsibilities
Run Logic/Physical synthesis using advanced techniques to generate netlists with optimized power, performance, and area. Perform logic equivalency checks for blocks/chip and analyze/debug the results. Conduct flat and hierarchical clock domain crossing analysis and collaborate with designers to address complex clock domain crossings. Execute flat and hierarchical reset domain crossing checks and understand reset architecture with designers. Perform RTL Lint and collaborate with designers to create waivers. Create timing constraints for synthesis. Develop automation scripts and methodologies for Front-end tools including LINT, CDC, RDC, SYN, LEC. Preferred Qualifications
Strong experience in Synthesis. Experience with LINT, Clock domain crossing, and reset domain crossing signoff. Proficiency in Logic equivalency checks. Knowledge of front-end ASIC flows. Experience in communicating across functional internal teams and vendors. Scripting and programming experience using Perl, TCL, Python, Cshell, and Make. Experience with SOC design integration and Front-end implementation. Knowledge of Timing/physical libraries and memories. Familiarity with Design Compiler, Fusion Compiler, Spyglass, Zero-in, Primetime, Formality, and Conformal LEC. Academic Credentials
BSEE or equivalent. MSEE preferred Location
Santa Clara, CA Benefits and Equal Opportunity
AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
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