Cadence
Overview
Cadence DDR PHY IP Front End Design team is hiring. Be part of a scope that involves developing firmware for DDR5 PHY using microcontrollers, collaborating with hardware designers and memory subsystem architects, and working with verification teams to co-verify firmware and hardware. Responsibilities
Develop firmware for DDR5 PHY using microcontrollers. Developing firmware in C typically involving bare-metal programming and developing low-level APIs on microcontrollers. Collaborate with hardware designers and memory subsystem architects to derive training algorithms and implement them. Collaborate with the verification team to deduce firmware-hardware co-verification plan. Develop and debug firmware in RTL-based hardware simulations (C + Verilog simulations). Develop and debug on Silicon bring-up boards. Required Skills
Good knowledge of DDR5 JEDEC spec, knowledge of different DIMM configurations and specifications. Relevant experience in developing bare-metal firmware for High-speed SerDes or Memory interface Physical Layer blocks. Good knowledge of C programming language for embedded software development and use of relevant IDE. Comfortable debugging RTL simulations involving firmware and microcontroller subsystem. Good knowledge of Shell/Perl/Python/TCL scripting. Good experience with Verification EDA Tools like simulators and waveform viewers. Seniority level
Mid-Senior level Employment type
Full-time Location
Austin, TX We’re doing work that matters. Help us solve what others can’t.
#J-18808-Ljbffr
Cadence DDR PHY IP Front End Design team is hiring. Be part of a scope that involves developing firmware for DDR5 PHY using microcontrollers, collaborating with hardware designers and memory subsystem architects, and working with verification teams to co-verify firmware and hardware. Responsibilities
Develop firmware for DDR5 PHY using microcontrollers. Developing firmware in C typically involving bare-metal programming and developing low-level APIs on microcontrollers. Collaborate with hardware designers and memory subsystem architects to derive training algorithms and implement them. Collaborate with the verification team to deduce firmware-hardware co-verification plan. Develop and debug firmware in RTL-based hardware simulations (C + Verilog simulations). Develop and debug on Silicon bring-up boards. Required Skills
Good knowledge of DDR5 JEDEC spec, knowledge of different DIMM configurations and specifications. Relevant experience in developing bare-metal firmware for High-speed SerDes or Memory interface Physical Layer blocks. Good knowledge of C programming language for embedded software development and use of relevant IDE. Comfortable debugging RTL simulations involving firmware and microcontroller subsystem. Good knowledge of Shell/Perl/Python/TCL scripting. Good experience with Verification EDA Tools like simulators and waveform viewers. Seniority level
Mid-Senior level Employment type
Full-time Location
Austin, TX We’re doing work that matters. Help us solve what others can’t.
#J-18808-Ljbffr