NVIDIA Corporation
Senior Memory Controller Verification Engineer
NVIDIA Corporation, Santa Clara, California, us, 95053
Senior Memory Controller Verification Engineer page is loaded## Senior Memory Controller Verification Engineerlocations:
US, CA, Santa Claratime type:
Full timeposted on:
Posted Todayjob requisition id:
JR2005266NVIDIA is seeking hardworking, motivated and creative Senior Verification Engineer for our Tegra SoC Memory Subsystem IP verification Team! At NVIDIA, we have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. In this position, you will partner with the design and architecture teams to help make the right implementation choices, craft and implement verification test plans, maintain regressions, close coverage and sign off design or both functional correctness and for meeting performance expectations. This position offers the opportunity to have a real impact on multiple product lines including consumer graphics, self-driving cars, HPC, cloud computing, and AI!**What you’ll be doing:*** Develop verification infrastructure (testbenches, BFMs, checkers, monitors, randoms)* Come up with, review and drive test plan execution for planned features* Understand the performance requirements of your IP, come up with, review and drive performance testplan for your IP* Ensure code and functional coverage of all the RTL which you will verify.* Work with and enable FPGA and software teams to ensure that software is tested.* Plan for and be involved with post-silicon verification and debug.**What we need to see:*** BS / MS or equivalent experience.* 3+ years of ASIC verification experience of complex design units displaying good attention to detail, teamwork, problem solving and shown success* Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).* Background with System Verilog and UVM based methodology for ASIC verification.**Ways to stand out from the crowd:*** Strong C/C++ programming experience* Prior Design or Verification experience of dynamic memory controllers (ddr{2, 3, 4, 5}, lpddr{2, 3,4,5, 6})* Strong debugging and problem solving skills.* Scripting knowledge (Python/Perl/shell).* Good interpersonal skills and ability & desire to work as a part of a team.#LI-HybridYour base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.You will also be eligible for equity and .Applications for this job will be accepted at least until October 5, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. #J-18808-Ljbffr
US, CA, Santa Claratime type:
Full timeposted on:
Posted Todayjob requisition id:
JR2005266NVIDIA is seeking hardworking, motivated and creative Senior Verification Engineer for our Tegra SoC Memory Subsystem IP verification Team! At NVIDIA, we have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. In this position, you will partner with the design and architecture teams to help make the right implementation choices, craft and implement verification test plans, maintain regressions, close coverage and sign off design or both functional correctness and for meeting performance expectations. This position offers the opportunity to have a real impact on multiple product lines including consumer graphics, self-driving cars, HPC, cloud computing, and AI!**What you’ll be doing:*** Develop verification infrastructure (testbenches, BFMs, checkers, monitors, randoms)* Come up with, review and drive test plan execution for planned features* Understand the performance requirements of your IP, come up with, review and drive performance testplan for your IP* Ensure code and functional coverage of all the RTL which you will verify.* Work with and enable FPGA and software teams to ensure that software is tested.* Plan for and be involved with post-silicon verification and debug.**What we need to see:*** BS / MS or equivalent experience.* 3+ years of ASIC verification experience of complex design units displaying good attention to detail, teamwork, problem solving and shown success* Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).* Background with System Verilog and UVM based methodology for ASIC verification.**Ways to stand out from the crowd:*** Strong C/C++ programming experience* Prior Design or Verification experience of dynamic memory controllers (ddr{2, 3, 4, 5}, lpddr{2, 3,4,5, 6})* Strong debugging and problem solving skills.* Scripting knowledge (Python/Perl/shell).* Good interpersonal skills and ability & desire to work as a part of a team.#LI-HybridYour base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.You will also be eligible for equity and .Applications for this job will be accepted at least until October 5, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. #J-18808-Ljbffr