Infobahn Softworld Inc
Overview
Job Title: ASIC/RTL Design Engineer Location: San Jose - Onsite Responsibilities
Lead and participate in the design of leading edge SoCs in advanced digital CMOS processes. Expose the designer to IPs including ARM cores, Ethernet, DDR, DMA, PCIe, SATA and internal AMD IPs. Contribute to all aspects of SoC design: chip definition, architecture development and modeling, micro-architectural specification development, conversion of specifications to logic implementation, verification, emulation, debug, synthesis, and timing closure. Interface with physical design execution, software, and silicon bring-up teams. Experience and Qualifications
SoC design experience with knowledge and hands-on experience in industry ASIC design flow including RTL coding, IP integration, debugging/verification, and supporting synthesis and timing closure. Experience with front-end quality checks such as Lint, CDC, and RDC; running, debugging, reporting, and driving cleanup. Working knowledge of ARM cores and other I/O standard interfaces. Approximately 10 years of experience, with flexibility for less experience. Bachelors in Electrical Engineering or Computer Engineering preferred. Seniority level
Mid-Senior level Employment type
Contract Job function
Engineering and Information Technology Industries
Software Development
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Job Title: ASIC/RTL Design Engineer Location: San Jose - Onsite Responsibilities
Lead and participate in the design of leading edge SoCs in advanced digital CMOS processes. Expose the designer to IPs including ARM cores, Ethernet, DDR, DMA, PCIe, SATA and internal AMD IPs. Contribute to all aspects of SoC design: chip definition, architecture development and modeling, micro-architectural specification development, conversion of specifications to logic implementation, verification, emulation, debug, synthesis, and timing closure. Interface with physical design execution, software, and silicon bring-up teams. Experience and Qualifications
SoC design experience with knowledge and hands-on experience in industry ASIC design flow including RTL coding, IP integration, debugging/verification, and supporting synthesis and timing closure. Experience with front-end quality checks such as Lint, CDC, and RDC; running, debugging, reporting, and driving cleanup. Working knowledge of ARM cores and other I/O standard interfaces. Approximately 10 years of experience, with flexibility for less experience. Bachelors in Electrical Engineering or Computer Engineering preferred. Seniority level
Mid-Senior level Employment type
Contract Job function
Engineering and Information Technology Industries
Software Development
#J-18808-Ljbffr