Rapidus Corporation US
Foundry Application Engineer
Rapidus Corporation US, California, Missouri, United States, 65018
Overview
As a “Foundry Applications Engineer”, you will play a critical role in helping customers adopt and integrate Process Design Kits (PDKs) into their design flows. You will support successful implementation through to tapeout, working closely with internal PDK development teams, ecosystem partners, and EDA vendors. Your insights will help shape future enablement strategies and technical roadmaps.
Key Responsibilities
Serve as the primary technical point of contact for customer PDK integration and adoption.
Provide expert guidance on PDK usage, focusing on layout design rules, DRC/LVS checks, fill insertion, RC extraction, floorplanning, place-and-route, PPA optimization, and analog design enablement.
Collaborate with EDA vendors, IP providers, and process development teams to align PDK content with evolving technology requirements and customer feedback.
Deliver customer insights and issue reports to internal PDK development and enablement teams. Contribute to prioritization of features and fixes and ensure timely communication with stakeholders.
Required Qualifications
Master’s degree in electrical engineering or a related STEM field.
10+ years of experience in semiconductor design or enablement.
Comprehensive knowledge of the full RTL-to-GDSII design flow, including floorplanning, synthesis, place and route, physical verification (DRC, LVS, antenna, fill, PERC), RC extraction, static timing, and reliability verification.
5+ years of hands-on experience in:
Physical verification and debugging using Siemens Calibre, Cadence Pegasus, or Synopsys ICV
RTL-to-GDS implementation using Synopsys Fusion Compiler or Cadence Innovus, with demonstrated technical leadership in design flow automation and tapeout execution.
Full-chip floorplanning ownership and/or full-chip tapeout verification ownership
Seniority level Mid-Senior level
Employment type Full-time
Job function Semiconductor Manufacturing
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As a “Foundry Applications Engineer”, you will play a critical role in helping customers adopt and integrate Process Design Kits (PDKs) into their design flows. You will support successful implementation through to tapeout, working closely with internal PDK development teams, ecosystem partners, and EDA vendors. Your insights will help shape future enablement strategies and technical roadmaps.
Key Responsibilities
Serve as the primary technical point of contact for customer PDK integration and adoption.
Provide expert guidance on PDK usage, focusing on layout design rules, DRC/LVS checks, fill insertion, RC extraction, floorplanning, place-and-route, PPA optimization, and analog design enablement.
Collaborate with EDA vendors, IP providers, and process development teams to align PDK content with evolving technology requirements and customer feedback.
Deliver customer insights and issue reports to internal PDK development and enablement teams. Contribute to prioritization of features and fixes and ensure timely communication with stakeholders.
Required Qualifications
Master’s degree in electrical engineering or a related STEM field.
10+ years of experience in semiconductor design or enablement.
Comprehensive knowledge of the full RTL-to-GDSII design flow, including floorplanning, synthesis, place and route, physical verification (DRC, LVS, antenna, fill, PERC), RC extraction, static timing, and reliability verification.
5+ years of hands-on experience in:
Physical verification and debugging using Siemens Calibre, Cadence Pegasus, or Synopsys ICV
RTL-to-GDS implementation using Synopsys Fusion Compiler or Cadence Innovus, with demonstrated technical leadership in design flow automation and tapeout execution.
Full-chip floorplanning ownership and/or full-chip tapeout verification ownership
Seniority level Mid-Senior level
Employment type Full-time
Job function Semiconductor Manufacturing
#J-18808-Ljbffr