Tenstorrent Inc.
RISC V Sr. Staff Engineer, CPU MidCore RTL Design Santa Clara, California, Unite
Tenstorrent Inc., Santa Clara, California, us, 95053
Overview
Tenstorrent is leading the industry on AI technology, focusing on performance, ease of use, and cost efficiency. We are building a high performance RISC-V CPU from scratch and are looking for contributors of all seniorities who value collaboration, curiosity, and solving hard problems. We are looking for a talented Design Verification engineer to join our CPU design team to define and implement the MidCore block for a high-performance CPU based on the RISC-V ISA. You’ll collaborate with DV, PD, and performance teams to deliver a functional, timing, and power-converged design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level. Who You Are
Experienced in Out-of-Order CPU microarchitecture with expertise in Rename, Scheduler, ROB, and Datapath. Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis. Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments. Background in microarchitecture definition, design specification, and performance-driven trade-off analysis. What We Need
Own RTL design and microarchitecture development for a portion of the MidCore block of a high-performance RISC-V CPU. Collaborate closely with DV, PD, and performance engineers to meet functional, timing, and power goals. Use innovative techniques to optimize power, performance, and area while driving RTL experiments and evaluating results. Partner with validation and test teams to ensure robust pre-silicon and post-silicon execution. Enhance RTL design environment, tools, and methodologies to improve development efficiency. What You Will Learn
End-to-end exposure to CPU design from microarchitecture through timing and power convergence. Hands-on experience optimizing Out-of-Order CPU designs in both pre-silicon and post-silicon phases. Integration of open-source and industry-standard tools to improve RTL flows and results. Work in a deeply technical, highly collaborative team solving cutting-edge CPU design challenges. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon eligibility to access U.S. export-controlled technology and compliance with applicable laws. If employment is not possible due to export laws, any offer of employment will be rescinded. Voluntary Information
Tenstorrent collects voluntary self-identification information for government reporting purposes. Providing this information is optional and will not affect hiring decisions. We do not discriminate on the basis of protected status under applicable law. See our Equal Employment Opportunity policy for more details.
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Tenstorrent is leading the industry on AI technology, focusing on performance, ease of use, and cost efficiency. We are building a high performance RISC-V CPU from scratch and are looking for contributors of all seniorities who value collaboration, curiosity, and solving hard problems. We are looking for a talented Design Verification engineer to join our CPU design team to define and implement the MidCore block for a high-performance CPU based on the RISC-V ISA. You’ll collaborate with DV, PD, and performance teams to deliver a functional, timing, and power-converged design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level. Who You Are
Experienced in Out-of-Order CPU microarchitecture with expertise in Rename, Scheduler, ROB, and Datapath. Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis. Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments. Background in microarchitecture definition, design specification, and performance-driven trade-off analysis. What We Need
Own RTL design and microarchitecture development for a portion of the MidCore block of a high-performance RISC-V CPU. Collaborate closely with DV, PD, and performance engineers to meet functional, timing, and power goals. Use innovative techniques to optimize power, performance, and area while driving RTL experiments and evaluating results. Partner with validation and test teams to ensure robust pre-silicon and post-silicon execution. Enhance RTL design environment, tools, and methodologies to improve development efficiency. What You Will Learn
End-to-end exposure to CPU design from microarchitecture through timing and power convergence. Hands-on experience optimizing Out-of-Order CPU designs in both pre-silicon and post-silicon phases. Integration of open-source and industry-standard tools to improve RTL flows and results. Work in a deeply technical, highly collaborative team solving cutting-edge CPU design challenges. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon eligibility to access U.S. export-controlled technology and compliance with applicable laws. If employment is not possible due to export laws, any offer of employment will be rescinded. Voluntary Information
Tenstorrent collects voluntary self-identification information for government reporting purposes. Providing this information is optional and will not affect hiring decisions. We do not discriminate on the basis of protected status under applicable law. See our Equal Employment Opportunity policy for more details.
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