Micron Technology
Principal Memory Sustaining Physical Design Engineer, HBM
Micron Technology, Richardson, Texas, United States, 75080
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that transform information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Micron’s Heterogeneous Integration Group (HIG) develops advanced memory solutions for AI and accelerated computing by designing and optimizing High Bandwidth Memory (HBM) products for AI/ML, HPC, and data-centric systems, collaborating across global engineering and product teams to deliver industry-leading performance, power efficiency, and reliability.
The HBM product family is growing due to high demand from industry-leading semiconductor companies. As a HBM Memory Physical Design Engineer in a sustaining role, you will work with teams like Design Engineering (DE), Product Engineering (PE), Process Integration (PI), Packaging, and Technology Development (TD) to evaluate silicon issues seen on all current HBM designs.
You will be responsible for supporting design and development of critical analog, mixed-signal, and digital block and full chip level integration from a physical design and layout design perspective. This includes creating floorplans that optimize circuit placement, signal routing, and power delivery, as well as delivering block-level layouts using advanced foundry process nodes.
Responsibilities:
Implement layout changes to resolve issues identified on current HBM designs on silicon and drive towards a timely and efficient tapeout. Interact with teams like DE, PE, PI, and TD to understand the challenges due to process limitations and propose layout solutions to alleviate the issues. Identify and flag design issues, performance problems, and opportunities to improve design performance and reduce power consumption. Optimize circuit placement, signal routing, and power delivery through floor plans. Deliver block-level (analog or mixed signal) layouts using advanced foundry process nodes if needed. Contribute to the development of new HBM product opportunities by assisting with the overall planning and optimization of Memory, Logic, and Analog circuits layout. Debug and identify root causes and solutions for pre-silicon and post-silicon issues encountered in current HBM products. Mentor new hires as needed. Minimum Qualifications:
Bachelor or Master’s degree in Electrical Engineering or related field. Proven significant experience of 8+ years with a BS or 6+ years with an MS. Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS. Good understanding of Analog Layout fundamentals. Understanding of timing/area/power/complexity trade-offs in DRAM or mixed-signal design. Firsthand experience crafting layout of analog and mixed signals. Preferred Qualifications:
Good verbal and written communication skills. A self-motivated, hard-working team player with diverse abilities and backgrounds. Excellent problem-solving and analytical skills. Proven track record of innovation and problem-solving in high-performance memory development. Prior experience with DRAM product bring-up and debug. Prior experience with package technologies (TSV, hybrid bonding, interposers, etc). Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity, or any other factor protected by applicable federal, state, or local laws.
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Implement layout changes to resolve issues identified on current HBM designs on silicon and drive towards a timely and efficient tapeout. Interact with teams like DE, PE, PI, and TD to understand the challenges due to process limitations and propose layout solutions to alleviate the issues. Identify and flag design issues, performance problems, and opportunities to improve design performance and reduce power consumption. Optimize circuit placement, signal routing, and power delivery through floor plans. Deliver block-level (analog or mixed signal) layouts using advanced foundry process nodes if needed. Contribute to the development of new HBM product opportunities by assisting with the overall planning and optimization of Memory, Logic, and Analog circuits layout. Debug and identify root causes and solutions for pre-silicon and post-silicon issues encountered in current HBM products. Mentor new hires as needed. Minimum Qualifications:
Bachelor or Master’s degree in Electrical Engineering or related field. Proven significant experience of 8+ years with a BS or 6+ years with an MS. Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS. Good understanding of Analog Layout fundamentals. Understanding of timing/area/power/complexity trade-offs in DRAM or mixed-signal design. Firsthand experience crafting layout of analog and mixed signals. Preferred Qualifications:
Good verbal and written communication skills. A self-motivated, hard-working team player with diverse abilities and backgrounds. Excellent problem-solving and analytical skills. Proven track record of innovation and problem-solving in high-performance memory development. Prior experience with DRAM product bring-up and debug. Prior experience with package technologies (TSV, hybrid bonding, interposers, etc). Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity, or any other factor protected by applicable federal, state, or local laws.
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