Experis
Our client, a leading organization in the technology and electronics industry, is seeking an IP Design Engineer to join their team. As an IP Design Engineer, you will be part of the Engineering Department supporting the Video Connectivity Systems team. The ideal candidate will demonstrate strong technical expertise, excellent communication skills, and a proactive approach to problem-solving, which will align successfully in the organization.
Job Title: IP Design Engineer
Location: Santa Clara, CA (Hybrid)
Duration: 06+ Months Contract
What's the Job?
Design and develop Register-Transfer Level (RTL) Intellectual Property (IP) focused on video connectivity subsystems. Participate in project definition, RTL design, and implementation activities for low latency video systems. Collaborate with cross-functional teams to ensure design specifications are met and integrated effectively. Implement resource optimization, clock domain crossing, and reset domain crossing techniques in RTL coding. Contribute to design documentation, architecture, and verification processes to ensure high-quality deliverables. What's Needed?
Proven experience working on Video domain IPs or Digital IPs with a focus on high-performance systems. Hands‑on experience with protocols such as MIPI CSI, MIPI DSI, DisplayPort, HDMI, or SDI at the IP level. Experience with AMD / Xilinx FPGA devices and Vivado toolchain for FPGA design and implementation. Strong skills in synthesizable Verilog / SystemVerilog RTL coding and familiarity with front‑end methodology flows. Knowledge of static timing analysis, CDC, synthesis flows, and formal verification techniques. What's in it for me?
Opportunity to work on cutting‑edge video connectivity technologies in a dynamic environment. Engagement with a collaborative and innovative team dedicated to technological excellence. Chance to develop your skills with advanced FPGA design tools and methodologies. Work in a supportive environment that values diversity and continuous learning. Competitive compensation aligned with your expertise and experience. If this is a role that interests you and you'd like to learn more, click apply now and a recruiter will be in touch with you to discuss this great opportunity. We look forward to speaking with you!
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Design and develop Register-Transfer Level (RTL) Intellectual Property (IP) focused on video connectivity subsystems. Participate in project definition, RTL design, and implementation activities for low latency video systems. Collaborate with cross-functional teams to ensure design specifications are met and integrated effectively. Implement resource optimization, clock domain crossing, and reset domain crossing techniques in RTL coding. Contribute to design documentation, architecture, and verification processes to ensure high-quality deliverables. What's Needed?
Proven experience working on Video domain IPs or Digital IPs with a focus on high-performance systems. Hands‑on experience with protocols such as MIPI CSI, MIPI DSI, DisplayPort, HDMI, or SDI at the IP level. Experience with AMD / Xilinx FPGA devices and Vivado toolchain for FPGA design and implementation. Strong skills in synthesizable Verilog / SystemVerilog RTL coding and familiarity with front‑end methodology flows. Knowledge of static timing analysis, CDC, synthesis flows, and formal verification techniques. What's in it for me?
Opportunity to work on cutting‑edge video connectivity technologies in a dynamic environment. Engagement with a collaborative and innovative team dedicated to technological excellence. Chance to develop your skills with advanced FPGA design tools and methodologies. Work in a supportive environment that values diversity and continuous learning. Competitive compensation aligned with your expertise and experience. If this is a role that interests you and you'd like to learn more, click apply now and a recruiter will be in touch with you to discuss this great opportunity. We look forward to speaking with you!
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