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Role Overview
Design and develop Register-Transfer Level (RTL) Intellectual Property (IP) focused on video connectivity subsystems. Responsibilities
Design and develop
Register-Transfer Level (RTL)
Intellectual Property (IP) with a focus on video connectivity subsystems. Contribute to
architecture, documentation, and implementation
of low-latency video systems. Perform
RTL coding
in Verilog/SystemVerilog for blocks specified by you or team members. Optimize designs for
resource utilization, clock and reset domain crossings , and overall performance. Collaborate closely with cross-functional engineering teams across global time zones. Required Skills & Experience
Strong hands-on experience with
RTL IP Design
using
Verilog/SystemVerilog . Proven experience working on
Video or Digital IPs . Deep understanding of one or more of these
protocols at the IP level: MIPI CSI / MIPI DSI / DisplayPort / HDMI / SDI Experience with
AMD/Xilinx FPGA architecture
and
Vivado toolchain . Solid understanding of
synthesis, lint, CDC, static timing analysis, and formal verification . Proficiency in
TCL, Perl, or Python
scripting is a plus. Knowledge of
SERDES architecture
is an added advantage. Strong analytical, communication, and collaboration skills. Seniority Level
Associate Employment Type
Contract Job Function
Information Technology Industries
Semiconductor Manufacturing
#J-18808-Ljbffr
Design and develop Register-Transfer Level (RTL) Intellectual Property (IP) focused on video connectivity subsystems. Responsibilities
Design and develop
Register-Transfer Level (RTL)
Intellectual Property (IP) with a focus on video connectivity subsystems. Contribute to
architecture, documentation, and implementation
of low-latency video systems. Perform
RTL coding
in Verilog/SystemVerilog for blocks specified by you or team members. Optimize designs for
resource utilization, clock and reset domain crossings , and overall performance. Collaborate closely with cross-functional engineering teams across global time zones. Required Skills & Experience
Strong hands-on experience with
RTL IP Design
using
Verilog/SystemVerilog . Proven experience working on
Video or Digital IPs . Deep understanding of one or more of these
protocols at the IP level: MIPI CSI / MIPI DSI / DisplayPort / HDMI / SDI Experience with
AMD/Xilinx FPGA architecture
and
Vivado toolchain . Solid understanding of
synthesis, lint, CDC, static timing analysis, and formal verification . Proficiency in
TCL, Perl, or Python
scripting is a plus. Knowledge of
SERDES architecture
is an added advantage. Strong analytical, communication, and collaboration skills. Seniority Level
Associate Employment Type
Contract Job Function
Information Technology Industries
Semiconductor Manufacturing
#J-18808-Ljbffr