Intel Corporation
Senior Silicon Design Engineer
Intel Central Engineering Group is expanding rapidly on its advanced technologies, serving OEMs, ODMs, and design partners. The Senior Silicon Design Engineer will act as the voice of the customer, driving product improvements and resolving issues across the entire product lifecycle.
Responsibilities
Perform physical design implementation of custom IP and SoC designs from RTL to GDS, creating a design database ready for manufacturing.
Conduct all aspects of the physical design flow, including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
Verify and signoff, including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
Analyze results and recommend fixes for current and future product architecture violations.
Possess expertise in structural and physical design, including clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and digital for timing (DFT) using industry standard EDA tools.
Optimize design to improve product level parameters such as power, frequency, and area.
Participate in development and improvement of physical design methodologies and flow automation.
Minimum Qualifications
Bachelor's degree in Electrical / Computer Engineering, Computer Science, or a STEM related field.
Experience leading a small team of engineers.
7+ years of experience with complex ASIC/SOC implementation.
Experience in system and processor architecture.
Experience designing and implementing complex blocks such as CPUs, GPUs, media blocks, and memory controllers.
Experience with System Verilog / SOC development environment.
Experience with scripting languages (PERL, TCL, or Python).
Experience with hardware validation techniques (formal verification, test and function verification).
Preferred Qualifications
Postgraduate degree in Electrical / Computer Engineering, Computer Science, or a STEM related field.
Experience with industry standard protocols (PCIE, USB, DDR, etc).
Experience with interaction of computer hardware with software.
Experience with low power / UPF implementation and verification techniques.
Experience with formal verification techniques.
Job Details Job type: Experienced Hire Shift: Shift 1 (United States of America) Primary location: US, Texas, Austin Additional locations: US, California, Santa Clara
EEO Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits & Compensation Annual Salary Range: $161,230.00 – $303,140.00 USD Compensation includes competitive pay, stock, bonuses, and benefits programs such as health, retirement, and vacation.
Work Model This role will require an on-site presence. Job posting details may change.
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Responsibilities
Perform physical design implementation of custom IP and SoC designs from RTL to GDS, creating a design database ready for manufacturing.
Conduct all aspects of the physical design flow, including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
Verify and signoff, including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
Analyze results and recommend fixes for current and future product architecture violations.
Possess expertise in structural and physical design, including clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and digital for timing (DFT) using industry standard EDA tools.
Optimize design to improve product level parameters such as power, frequency, and area.
Participate in development and improvement of physical design methodologies and flow automation.
Minimum Qualifications
Bachelor's degree in Electrical / Computer Engineering, Computer Science, or a STEM related field.
Experience leading a small team of engineers.
7+ years of experience with complex ASIC/SOC implementation.
Experience in system and processor architecture.
Experience designing and implementing complex blocks such as CPUs, GPUs, media blocks, and memory controllers.
Experience with System Verilog / SOC development environment.
Experience with scripting languages (PERL, TCL, or Python).
Experience with hardware validation techniques (formal verification, test and function verification).
Preferred Qualifications
Postgraduate degree in Electrical / Computer Engineering, Computer Science, or a STEM related field.
Experience with industry standard protocols (PCIE, USB, DDR, etc).
Experience with interaction of computer hardware with software.
Experience with low power / UPF implementation and verification techniques.
Experience with formal verification techniques.
Job Details Job type: Experienced Hire Shift: Shift 1 (United States of America) Primary location: US, Texas, Austin Additional locations: US, California, Santa Clara
EEO Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits & Compensation Annual Salary Range: $161,230.00 – $303,140.00 USD Compensation includes competitive pay, stock, bonuses, and benefits programs such as health, retirement, and vacation.
Work Model This role will require an on-site presence. Job posting details may change.
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