Akkodis
Silicon Design Verification Engineer (II)
We are seeking a contract Silicon Design Verification Engineer for a remote position in California. The pay range is $100 to $125 per hour. This role offers a competitive hourly rate with flexibility to discuss total compensation based on experience, education, geographic location, and other factors.
As a Silicon Design Verification Engineer, you complete end‑to‑end tasks that are integrated into an overarching project, with minimal assistance from more senior team members. You make larger, mostly independent technical contributions by planning, managing, and executing your own priorities, selecting appropriate methods to most effectively achieve verification goals and objectives. You typically verify a piece of a major functional block within an IP. You demonstrate deep understanding of Design Verification and possess proficient knowledge of the hardware engineering process to deliver verified designs.
Responsibilities
Apply verification techniques and methodologies to verify designs, with minimal guidance (mostly independently).
Apply verification tools and languages (e.g., SystemVerilog) to verify designs, with minimal guidance (mostly independently).
Develop test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation can be easily understood and used, with minimal guidance (mostly independently).
Work closely with architecture and designers to help verify the functional correctness of the logic design with minimal guidance (mostly independently).
Collaborate with cross‑functional teams to debug failures (e.g., boards, software, manufacturing, design, thermal issues).
SV coding skills.
Simulation‑based verification techniques, methodology, and experience.
Scripting and infrastructure.
Domain‑specific knowledge.
Testbench components and techniques.
UVM coding skills.
SVA coding skills.
Formal verification techniques, methodology, and experience.
Communication and comprehension.
Problem‑solving.
Equal Opportunity Employer We are an equal opportunity employer. Veterans and disabled applicants are encouraged to apply.
Benefits Benefit offerings available include medical, dental, vision, life insurance, short‑term disability, additional voluntary benefits, an EAP program, commuter benefits, and a 401(k) plan. Our benefit offerings provide flexibility to choose the type of coverage that meets individual needs. Associate may be eligible for paid leave including paid sick leave and holiday pay where applicable.
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As a Silicon Design Verification Engineer, you complete end‑to‑end tasks that are integrated into an overarching project, with minimal assistance from more senior team members. You make larger, mostly independent technical contributions by planning, managing, and executing your own priorities, selecting appropriate methods to most effectively achieve verification goals and objectives. You typically verify a piece of a major functional block within an IP. You demonstrate deep understanding of Design Verification and possess proficient knowledge of the hardware engineering process to deliver verified designs.
Responsibilities
Apply verification techniques and methodologies to verify designs, with minimal guidance (mostly independently).
Apply verification tools and languages (e.g., SystemVerilog) to verify designs, with minimal guidance (mostly independently).
Develop test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation can be easily understood and used, with minimal guidance (mostly independently).
Work closely with architecture and designers to help verify the functional correctness of the logic design with minimal guidance (mostly independently).
Collaborate with cross‑functional teams to debug failures (e.g., boards, software, manufacturing, design, thermal issues).
SV coding skills.
Simulation‑based verification techniques, methodology, and experience.
Scripting and infrastructure.
Domain‑specific knowledge.
Testbench components and techniques.
UVM coding skills.
SVA coding skills.
Formal verification techniques, methodology, and experience.
Communication and comprehension.
Problem‑solving.
Equal Opportunity Employer We are an equal opportunity employer. Veterans and disabled applicants are encouraged to apply.
Benefits Benefit offerings available include medical, dental, vision, life insurance, short‑term disability, additional voluntary benefits, an EAP program, commuter benefits, and a 401(k) plan. Our benefit offerings provide flexibility to choose the type of coverage that meets individual needs. Associate may be eligible for paid leave including paid sick leave and holiday pay where applicable.
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