GPU Logic Design Engineer

Intel’s Discrete Graphics Engineering (DGE) organization develops cutting-edge discrete graphics products for gaming and AI. If you are an engineer with strong technical and communication skills who thrives in a fast-paced environment with abundant learning opportunities, you are the ideal candidate for this role. You will be responsible for designing and/or integrating IP for a discrete graphics SoC. Your responsibilities include: Creating designs to improve product KPIs for discrete graphics products. Collaborating with SoC architecture and platform teams to establish silicon requirements. Making design trade-offs balancing risk, area, power, performance, validation complexity, and schedule. Developing microarchitectural specifications for designs. Working with external vendors on tools or IPs for micro-architecture development, design, and qualification. Driving vendor methodology to meet silicon design standards. Architecting area and power-efficient, low-latency designs with scalability and flexibility. Designing RTL logic with power and area efficiency, supporting verification. Running tools to ensure lint-free, CDC/RDC clean designs, and VCLP compliance. Managing synthesis, timing constraints, and achieving successful tape-outs with first-pass silicon. Hands-on experience with FPGA emulation, silicon bring-up, characterization, and debugging. Collaborating across teams and vendors to resolve architectural and implementation challenges within schedules. Possessing strong verbal and written communication skills. Understanding Verilog and SystemVerilog, synthesizable RTL. Knowledge of modern design techniques, energy-efficient logic design, and power analysis. Experience with power estimation, modeling, profiling, and post-silicon power correlation. Background in computer architecture. Familiarity with bus fabric protocols (e.g., APB, AHB, AXI). Knowledge of power management with multiple domains, UPF, power state tables. Understanding of lint, CDC, RDC tools, timing constraints, and connectivity tools. Understanding of key SoC design elements like arbiters, async FIFOs, DMAs, controllers. Knowledge of asynchronous clock crossing methodologies. Proven track record of bringing logic designs into high-volume production. Ability to work well in teams and meet ambitious schedules. Self-motivated and well-organized. Qualifications: BS degree with 5+ years of relevant industry experience. This position is located in the US, with opportunities in California, Arizona, and Oregon. The role requires on-site presence. The salary range is $214,730 to $303,140, depending on experience and location. We offer a comprehensive benefits package, including health, retirement, bonuses, and stock options. More details can be found

here . This job is active and accepting applications.

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