AMD
Overview
DDR / Memory PHY Post Silicon Validation Engineer at AMD Join to apply for the
DDR / Memory PHY Post Silicon Validation Engineer
role at
AMD Compensation
Base pay range: $171,200.00/yr - $256,800.00/yr The Role
As a member of the IO and Circuit Technologies Group, you will help bring to life cutting-edge designs. As part of the High-Speed IO Interface IP engineering team, you will be part of the Memory sub-team working closely with Architecture, IP design, Physical Design, SoC, Platform, Product, and other engineering teams to productize best-in-class HBM (high bandwidth memory)/DDR/LPDDR memory interface IPs on silicon. The Person
A successful candidate will work with senior silicon design engineers and leaders. The candidate will be highly technical and detail-oriented, possessing good communication, strong analytical and problem-solving skills involving post-silicon debug and pre-silicon issues. Key Responsibilities
Provide systems engineering and post-silicon support for HBM/DDR/LPDDR Memory interface IP. New products bring-up support from first silicon in the lab through initial production. Triage observations from silicon validation, and help debug issues with ATE, Platform, Firmware, and Characterization / Compliance teams. Provide expertise and support in silicon design, process, and integration flows for Memory Interface IP. Pre-Silicon engagement with internal and external PHY design teams, Platform, ATE, IP design, and Firmware teams. Perform and review analog circuit and mixed-signal design/analysis for high-speed I/O and Memory Interface IP in advanced process technologies. Preferred Experience
High-speed I/O design experience, including understanding of Tx (transceiver), Rx (Receiver), PLL/DLL, Clocking, Equalization techniques and circuits, Training algorithms and Firmware Python and/or Perl programming for test scripts, data analysis, FW code creation/debug Familiarity with UNIX and Windows environments Ability to adapt and learn new toolsets and frameworks Basic understanding of Verilog RTL, digital circuits, and the backend physical flow Laboratory experience with equipment such as oscilloscopes, signal generators, BERT, logic analyzers, etc. Academic Credentials
Bachelors or Masters degree in Computer Engineering or Electrical Engineering Location
Austin, TX Benefits and Equal Opportunity
Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
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DDR / Memory PHY Post Silicon Validation Engineer at AMD Join to apply for the
DDR / Memory PHY Post Silicon Validation Engineer
role at
AMD Compensation
Base pay range: $171,200.00/yr - $256,800.00/yr The Role
As a member of the IO and Circuit Technologies Group, you will help bring to life cutting-edge designs. As part of the High-Speed IO Interface IP engineering team, you will be part of the Memory sub-team working closely with Architecture, IP design, Physical Design, SoC, Platform, Product, and other engineering teams to productize best-in-class HBM (high bandwidth memory)/DDR/LPDDR memory interface IPs on silicon. The Person
A successful candidate will work with senior silicon design engineers and leaders. The candidate will be highly technical and detail-oriented, possessing good communication, strong analytical and problem-solving skills involving post-silicon debug and pre-silicon issues. Key Responsibilities
Provide systems engineering and post-silicon support for HBM/DDR/LPDDR Memory interface IP. New products bring-up support from first silicon in the lab through initial production. Triage observations from silicon validation, and help debug issues with ATE, Platform, Firmware, and Characterization / Compliance teams. Provide expertise and support in silicon design, process, and integration flows for Memory Interface IP. Pre-Silicon engagement with internal and external PHY design teams, Platform, ATE, IP design, and Firmware teams. Perform and review analog circuit and mixed-signal design/analysis for high-speed I/O and Memory Interface IP in advanced process technologies. Preferred Experience
High-speed I/O design experience, including understanding of Tx (transceiver), Rx (Receiver), PLL/DLL, Clocking, Equalization techniques and circuits, Training algorithms and Firmware Python and/or Perl programming for test scripts, data analysis, FW code creation/debug Familiarity with UNIX and Windows environments Ability to adapt and learn new toolsets and frameworks Basic understanding of Verilog RTL, digital circuits, and the backend physical flow Laboratory experience with equipment such as oscilloscopes, signal generators, BERT, logic analyzers, etc. Academic Credentials
Bachelors or Masters degree in Computer Engineering or Electrical Engineering Location
Austin, TX Benefits and Equal Opportunity
Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
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