Renesas Electronics Corporation
Sr Staff Verification Engineer – SoC/IP Design Verification
Renesas Electronics Corporation, New York, New York, us, 10261
Job Description
We are seeking a
Senior Staff Verification Engineer
to lead and contribute to the functional verification of
complex SoC and IP designs
for next-generation
AI, HPC, and data center
products. The ideal candidate has extensive experience in
UVM/SystemVerilog , SoC and IP-level verification, and is passionate about ensuring
first-pass silicon success . This role involves defining verification strategies, developing scalable environments, and collaborating cross-functionally with architecture, design, and software teams.
Experience with Virtual Modeling, SystemC, and TLM
is a
plus , enabling advanced verification and early system-level validation. Qualifications
Education & Experience
B.S./M.S. in Electrical Engineering, Computer Engineering, or related field. 8+ years of experience
in IP/SoC verification with a proven track record of successful silicon delivery.
Technical Expertise
Deep knowledge of
UVM/SystemVerilog
for testbench development and verification IP integration. Strong understanding of SoC architecture and protocols such as
DDR5, HBM3, PCIe Gen6, CXL 3.0 , and other high-speed interfaces. Expertise in
coverage-driven verification , constrained-random testing, and assertion-based verification. Proficient in
debugging RTL, testbenches, and simulation failures
using industry-standard tools.
Tools & Languages
Hands-on experience with simulation tools (VCS, Xcelium, Questa, etc.), waveform viewers, coverage tools, and automation scripting (Python, Perl, TCL).
Preferred/Additional Skills Virtual Modeling and System-Level Verification
Familiarity with
SystemC
and
Transaction-Level Modeling (TLM)
for virtual prototyping and early system validation. Experience developing or using
virtual platforms
for hardware/software co-verification is a strong plus.
Emulation & Prototyping
Exposure to
emulation platforms
(Palladium, ZeBu) and FPGA-based prototyping for system-level validation and performance analysis.
Software Co-verification
Experience working alongside firmware/software teams for
pre-silicon software validation
and early driver/OS bring-up.
Low-Power and DFT Verification
Knowledge of
power-aware verification
(UPF/CPF) and
DFT validation methodologies
is desirable.
Key Responsibilities
Verification Planning & Execution
Lead the definition, development, and execution of
comprehensive verification plans
at IP and SoC levels. Develop
UVM/SystemVerilog-based testbenches , including stimulus generation, checkers, and monitors for advanced SoC designs. Drive
coverage-driven verification
processes, ensuring functional and code coverage goals are met.
Cross-Functional Collaboration
Collaborate with
architecture, RTL design, firmware, software, and emulation teams
to define verification requirements and ensure comprehensive test coverage. Participate in
design and architecture reviews , providing critical feedback on functionality, testability, and performance considerations.
Debug & Issue Resolution
Lead
debug efforts
on complex SoC and IP issues through simulation, emulation, and FPGA prototypes. Perform
root-cause analysis
and drive issues to closure in partnership with cross-disciplinary teams.
Methodology & Infrastructure Development
Enhance and maintain
verification methodologies , including reusable verification IP, automation scripts, and regression infrastructure. Evaluate and adopt new tools and verification technologies to improve quality and efficiency.
Leadership & Mentorship
Provide
technical guidance and mentorship
to junior verification engineers. Lead
verification reviews and strategy discussions , ensuring high technical standards and best practices.
Company Description
Renesas is one of the top global semiconductor companies. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.
#J-18808-Ljbffr
We are seeking a
Senior Staff Verification Engineer
to lead and contribute to the functional verification of
complex SoC and IP designs
for next-generation
AI, HPC, and data center
products. The ideal candidate has extensive experience in
UVM/SystemVerilog , SoC and IP-level verification, and is passionate about ensuring
first-pass silicon success . This role involves defining verification strategies, developing scalable environments, and collaborating cross-functionally with architecture, design, and software teams.
Experience with Virtual Modeling, SystemC, and TLM
is a
plus , enabling advanced verification and early system-level validation. Qualifications
Education & Experience
B.S./M.S. in Electrical Engineering, Computer Engineering, or related field. 8+ years of experience
in IP/SoC verification with a proven track record of successful silicon delivery.
Technical Expertise
Deep knowledge of
UVM/SystemVerilog
for testbench development and verification IP integration. Strong understanding of SoC architecture and protocols such as
DDR5, HBM3, PCIe Gen6, CXL 3.0 , and other high-speed interfaces. Expertise in
coverage-driven verification , constrained-random testing, and assertion-based verification. Proficient in
debugging RTL, testbenches, and simulation failures
using industry-standard tools.
Tools & Languages
Hands-on experience with simulation tools (VCS, Xcelium, Questa, etc.), waveform viewers, coverage tools, and automation scripting (Python, Perl, TCL).
Preferred/Additional Skills Virtual Modeling and System-Level Verification
Familiarity with
SystemC
and
Transaction-Level Modeling (TLM)
for virtual prototyping and early system validation. Experience developing or using
virtual platforms
for hardware/software co-verification is a strong plus.
Emulation & Prototyping
Exposure to
emulation platforms
(Palladium, ZeBu) and FPGA-based prototyping for system-level validation and performance analysis.
Software Co-verification
Experience working alongside firmware/software teams for
pre-silicon software validation
and early driver/OS bring-up.
Low-Power and DFT Verification
Knowledge of
power-aware verification
(UPF/CPF) and
DFT validation methodologies
is desirable.
Key Responsibilities
Verification Planning & Execution
Lead the definition, development, and execution of
comprehensive verification plans
at IP and SoC levels. Develop
UVM/SystemVerilog-based testbenches , including stimulus generation, checkers, and monitors for advanced SoC designs. Drive
coverage-driven verification
processes, ensuring functional and code coverage goals are met.
Cross-Functional Collaboration
Collaborate with
architecture, RTL design, firmware, software, and emulation teams
to define verification requirements and ensure comprehensive test coverage. Participate in
design and architecture reviews , providing critical feedback on functionality, testability, and performance considerations.
Debug & Issue Resolution
Lead
debug efforts
on complex SoC and IP issues through simulation, emulation, and FPGA prototypes. Perform
root-cause analysis
and drive issues to closure in partnership with cross-disciplinary teams.
Methodology & Infrastructure Development
Enhance and maintain
verification methodologies , including reusable verification IP, automation scripts, and regression infrastructure. Evaluate and adopt new tools and verification technologies to improve quality and efficiency.
Leadership & Mentorship
Provide
technical guidance and mentorship
to junior verification engineers. Lead
verification reviews and strategy discussions , ensuring high technical standards and best practices.
Company Description
Renesas is one of the top global semiconductor companies. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.
#J-18808-Ljbffr