SPACE EXPLORATION TECHNOLOGIES CORP
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
SPACE EXPLORATION TECHNOLOGIES CORP, Irvine, California, United States, 92713
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) – Irvine, CA
SpaceX was founded with a future where humanity explores the stars. We are developing technologies to enable human life on Mars and to deploy Starlink, the world’s most advanced broadband internet system. We are seeking a motivated, proactive, and intellectually curious engineer to work with cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). You will help develop cutting-edge silicon for space and ground infrastructure, enabling connectivity globally. Responsibilities
Perform partition synthesis and physical implementation steps (synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks) Develop/improve physical design methodologies and automation scripts for various implementation steps Collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area targets, and explore RTL/design tradeoffs Resolve design/timing/congestion and flow issues, identify solutions, and drive execution Run, debug, and fix signoff closure issues in STA, noise, logic equivalency, physical verification, electromigration and voltage drop Basic Qualifications
Bachelor’s degree in electrical engineering, computer engineering or computer science 5+ years of ASIC and/or physical design flow development experience in industry Preferred Skills and Experience
Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows Strong experience with industry standard EDA tools and understanding of their capabilities and underlying algorithms Knowledge of deep sub-micron FinFET and CMOS solid state physics Knowledge of CMOS digital design principles, standard cells and libraries Understanding of CMOS power dissipation in deep submicron processes (leakage/dynamic) Familiarity with CMOS analog circuit and physical design Knowledge of DFT/Scan/MBIST/LBIST and their impact on physical design flows Self-driven, can-do attitude; willing to learn and work in a dynamic team Additional Requirements
Must be willing to work extended hours and weekends as needed Compensation and Benefits
Pay range: Physical Design Engineer/Senior: $160,000 - $220,000 per year. Actual level and base salary determined on a case-by-case basis based on job-related knowledge, education, and experience. Base salary is part of total rewards, which may include long-term incentives (stock or stock options), discretionary bonuses, and Employee Stock Purchase Plan. Benefits include medical, vision, dental, 401(k), disability and life insurance, paid parental leave, paid vacation, holidays, and sick leave for exempt employees. Export regulations: To conform to U.S. Government export regulations, applicant must be a U.S. citizen or national, a U.S. lawful permanent resident, or eligible to obtain required authorizations from the U.S. Department of State. SpaceX is an Equal Opportunity Employer. Employment is based on merit, competence and qualifications and will not be influenced by race, color, religion, gender, national origin, veteran status, disability, age, sexual orientation, gender identity, marital status, or any other protected status. EEO information is available upon request. Applications: SpaceX is committed to a fair and accessible hiring process. For accommodation requests, contact EEOCompliance@spacex.com.
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SpaceX was founded with a future where humanity explores the stars. We are developing technologies to enable human life on Mars and to deploy Starlink, the world’s most advanced broadband internet system. We are seeking a motivated, proactive, and intellectually curious engineer to work with cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). You will help develop cutting-edge silicon for space and ground infrastructure, enabling connectivity globally. Responsibilities
Perform partition synthesis and physical implementation steps (synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks) Develop/improve physical design methodologies and automation scripts for various implementation steps Collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area targets, and explore RTL/design tradeoffs Resolve design/timing/congestion and flow issues, identify solutions, and drive execution Run, debug, and fix signoff closure issues in STA, noise, logic equivalency, physical verification, electromigration and voltage drop Basic Qualifications
Bachelor’s degree in electrical engineering, computer engineering or computer science 5+ years of ASIC and/or physical design flow development experience in industry Preferred Skills and Experience
Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows Strong experience with industry standard EDA tools and understanding of their capabilities and underlying algorithms Knowledge of deep sub-micron FinFET and CMOS solid state physics Knowledge of CMOS digital design principles, standard cells and libraries Understanding of CMOS power dissipation in deep submicron processes (leakage/dynamic) Familiarity with CMOS analog circuit and physical design Knowledge of DFT/Scan/MBIST/LBIST and their impact on physical design flows Self-driven, can-do attitude; willing to learn and work in a dynamic team Additional Requirements
Must be willing to work extended hours and weekends as needed Compensation and Benefits
Pay range: Physical Design Engineer/Senior: $160,000 - $220,000 per year. Actual level and base salary determined on a case-by-case basis based on job-related knowledge, education, and experience. Base salary is part of total rewards, which may include long-term incentives (stock or stock options), discretionary bonuses, and Employee Stock Purchase Plan. Benefits include medical, vision, dental, 401(k), disability and life insurance, paid parental leave, paid vacation, holidays, and sick leave for exempt employees. Export regulations: To conform to U.S. Government export regulations, applicant must be a U.S. citizen or national, a U.S. lawful permanent resident, or eligible to obtain required authorizations from the U.S. Department of State. SpaceX is an Equal Opportunity Employer. Employment is based on merit, competence and qualifications and will not be influenced by race, color, religion, gender, national origin, veteran status, disability, age, sexual orientation, gender identity, marital status, or any other protected status. EEO information is available upon request. Applications: SpaceX is committed to a fair and accessible hiring process. For accommodation requests, contact EEOCompliance@spacex.com.
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