FPGA RTL Design Engineer

Job Title: FPGA RTL Design Engineer – Board Debug Expert Location:

Santa Clara, CA

Is your CV ready If so, and you are confident this is the role for you, make sure to apply asap. Duration:

1 Year (Contract) Experience:

6–12 Years Job Description: We are seeking a

highly skilled FPGA RTL Design Engineer

with strong hands-on experience in

Quartus-based FPGA design, IP verification, and board-level debug

. The ideal candidate will work on complex high-speed and precision FPGA systems, taking designs from concept through implementation, bring-up, and validation. Key Responsibilities: Develop and implement

FPGA RTL designs

using Verilog/VHDL/SystemVerilog. Target and optimize designs for

Intel/Altera Quartus FPGA platforms

. Perform

IP integration, verification, and debug

at block and system level. Conduct

board bring-up, power/clock validation, and signal integrity analysis

. Debug and validate FPGA designs using

SignalTap, ChipScope, oscilloscopes, and logic analyzers

. Collaborate with hardware and system teams to ensure functional validation and performance optimization. Required Skills: 6–12 years of FPGA design experience. Strong proficiency in

RTL design and simulation

(Verilog/VHDL/SystemVerilog). Hands-on experience with

Quartus, Vivado, and related FPGA toolchains

. Expertise in

Board Debug and Hardware Bring-up

. Experience with lab tools (oscilloscope, logic analyzer, multimeter). Solid understanding of

high-speed interfaces

(DDR, PCIe, SPI, I2C, etc.). Excellent problem-solving and communication skills. Preferred: Experience in

IP verification and FPGA prototyping

. Familiarity with

timing closure, floor planning, and signal integrity

. Bachelor’s or Master’s degree in

Electrical or Electronics Engineering

.