Conductor
Senior Staff Engineer, Serdes Layout Design
Conductor, San Jose, California, United States, 95199
San Jose, California, United States
Samsung Semiconductor Inc. (SSI)
is advancing the world’s technology. As a leader in memory, system, LSI, and LCD technologies, our U.S. teams contribute to breakthroughs in 5G, SOC, memory, and display. We’re dedicated to empowering people to be their true selves and building a better tomorrow for employees, customers, partners, and communities.
Location Daily onsite presence at our San Jose, CA headquarters in alignment with our Flexible Work policy.
What You’ll Do As a senior high‑speed mixed‑signal layout/analog engineer, you will work with circuit designers located in San Jose, California, USA to accomplish layout tasks for High Speed RX, TX, PLL, CDR, and analog reference circuits. You will optimize the performance and power consumption of SERDES analog PHY and determine the chip floorplan.
Collaborate with remote circuit designers to develop floorplan strategies that optimize parasites, reduce area, and improve high‑speed SERDES/analog performance.
Estimate schedules and develop plans to complete tasks within dedicated timeframes.
Read design documents from the foundry and resolve issues such as latch‑up and DRC.
Perform custom layout using Virtuoso and achieve clean LVS/DRC.
Use CAD tools including Virtuoso, Calibre LVS, DRC, SkillCad, and similar.
Have experience with chip‑level design, e.g., bump, pad, and ESD strategies.
Communicate effectively with circuit designers and design leads.
What You Bring
Bachelor's degree with 15+ years of experience, Master's with 13+ years, or Ph.D. with 10+ years.
Expertise in RF/analog/mixed‑signal/serdes layout design of deep sub‑micron CMOS circuits, including FinFET and GAA technologies.
High proficiency in interpreting Calibre DRC, ERC, and LVS reports.
Strong analog/mixed‑signal layout skills for high‑speed I/O blocks such as comparators, transmitters, receivers, and PLLs.
Experience with Cadence or Mentor Graphics layout tools.
Excellent communication skills for schedule planning and collaboration.
Experience leading complex layout projects through successful tape‑out.
Programming knowledge in Skill, Perl, and/or Python (bonus).
A collaborative mindset, inclusive attitude, and resilience in learning and problem‑solving.
Benefits Base Pay Range: $180,950 – $289,050 USD. Our compensation includes incentive opportunities tied to individual and company performance.
Benefits include medical, dental, vision, 401(k), paid time off, family support programs, fertility and adoption assistance, travel support, mental health resources, on‑site gym, and flexible work options.
Equal Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, national origin, political affiliation, or veteran status. Comprehensive accommodations are provided throughout our recruitment processes.
We do not accept unsolicited resumes. Only authorized recruitment agencies with a current valid agreement may submit resumes.
We prohibit the use of generative AI tools for misrepresenting a candidate’s true skills. All responses must reflect genuine abilities and experience.
Applicant Privacy Policy: https://semiconductor.samsung.com/about-us/careers/us/privacy/
#J-18808-Ljbffr
Samsung Semiconductor Inc. (SSI)
is advancing the world’s technology. As a leader in memory, system, LSI, and LCD technologies, our U.S. teams contribute to breakthroughs in 5G, SOC, memory, and display. We’re dedicated to empowering people to be their true selves and building a better tomorrow for employees, customers, partners, and communities.
Location Daily onsite presence at our San Jose, CA headquarters in alignment with our Flexible Work policy.
What You’ll Do As a senior high‑speed mixed‑signal layout/analog engineer, you will work with circuit designers located in San Jose, California, USA to accomplish layout tasks for High Speed RX, TX, PLL, CDR, and analog reference circuits. You will optimize the performance and power consumption of SERDES analog PHY and determine the chip floorplan.
Collaborate with remote circuit designers to develop floorplan strategies that optimize parasites, reduce area, and improve high‑speed SERDES/analog performance.
Estimate schedules and develop plans to complete tasks within dedicated timeframes.
Read design documents from the foundry and resolve issues such as latch‑up and DRC.
Perform custom layout using Virtuoso and achieve clean LVS/DRC.
Use CAD tools including Virtuoso, Calibre LVS, DRC, SkillCad, and similar.
Have experience with chip‑level design, e.g., bump, pad, and ESD strategies.
Communicate effectively with circuit designers and design leads.
What You Bring
Bachelor's degree with 15+ years of experience, Master's with 13+ years, or Ph.D. with 10+ years.
Expertise in RF/analog/mixed‑signal/serdes layout design of deep sub‑micron CMOS circuits, including FinFET and GAA technologies.
High proficiency in interpreting Calibre DRC, ERC, and LVS reports.
Strong analog/mixed‑signal layout skills for high‑speed I/O blocks such as comparators, transmitters, receivers, and PLLs.
Experience with Cadence or Mentor Graphics layout tools.
Excellent communication skills for schedule planning and collaboration.
Experience leading complex layout projects through successful tape‑out.
Programming knowledge in Skill, Perl, and/or Python (bonus).
A collaborative mindset, inclusive attitude, and resilience in learning and problem‑solving.
Benefits Base Pay Range: $180,950 – $289,050 USD. Our compensation includes incentive opportunities tied to individual and company performance.
Benefits include medical, dental, vision, 401(k), paid time off, family support programs, fertility and adoption assistance, travel support, mental health resources, on‑site gym, and flexible work options.
Equal Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, national origin, political affiliation, or veteran status. Comprehensive accommodations are provided throughout our recruitment processes.
We do not accept unsolicited resumes. Only authorized recruitment agencies with a current valid agreement may submit resumes.
We prohibit the use of generative AI tools for misrepresenting a candidate’s true skills. All responses must reflect genuine abilities and experience.
Applicant Privacy Policy: https://semiconductor.samsung.com/about-us/careers/us/privacy/
#J-18808-Ljbffr