IC Resources
Senior IC Layout Engineer
Join IC Resources to work as a Senior IC Layout Engineer for one of our leading Semiconductor clients based in Reading, Berkshire.
As the Senior IC Layout Engineer, you will own the custom layout and verification of analog circuits, cells, blocks, and IP for multi‑Gigabit high speed SerDes up to and beyond 28Gb/s and/or memory IO in advanced semiconductor technology nodes.
Responsibilities
Own custom layout and verification of analog circuits, cells, blocks, and IP for high speed SerDes and memory IO.
Lead chip layout activities and collaborate with design and verification teams.
Apply high‑speed layout techniques, matching constraints, and power grid design.
Extract and model parasitics, EM, IR drop and ESD requirements.
Qualifications
Experience in custom analog layout of circuits and blocks for high speed serial data‑link transceivers or high frequency circuits.
Strong layout knowledge of amplifiers, oscillators, PLLs, DLLs, buffers, regulators, filters and data converters.
Proficiency in modern semiconductor process technologies (28nm, 14/16nm, 7nm) and EDA tools (Cadence Virtuoso, Spectre/HSpice, Calibre/PVS, DRC/LVS).
Background in high‑speed design, EM, IR drop and ESD mitigation.
Experienced Analog IC Layout Engineer with a background working on high speed designs.
We offer a competitive salary, benefits package (including pension and private medical), visa sponsorship and relocation assistance where required.
Take the next step in your career — contact Caroline Pye today for more details or to apply.
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As the Senior IC Layout Engineer, you will own the custom layout and verification of analog circuits, cells, blocks, and IP for multi‑Gigabit high speed SerDes up to and beyond 28Gb/s and/or memory IO in advanced semiconductor technology nodes.
Responsibilities
Own custom layout and verification of analog circuits, cells, blocks, and IP for high speed SerDes and memory IO.
Lead chip layout activities and collaborate with design and verification teams.
Apply high‑speed layout techniques, matching constraints, and power grid design.
Extract and model parasitics, EM, IR drop and ESD requirements.
Qualifications
Experience in custom analog layout of circuits and blocks for high speed serial data‑link transceivers or high frequency circuits.
Strong layout knowledge of amplifiers, oscillators, PLLs, DLLs, buffers, regulators, filters and data converters.
Proficiency in modern semiconductor process technologies (28nm, 14/16nm, 7nm) and EDA tools (Cadence Virtuoso, Spectre/HSpice, Calibre/PVS, DRC/LVS).
Background in high‑speed design, EM, IR drop and ESD mitigation.
Experienced Analog IC Layout Engineer with a background working on high speed designs.
We offer a competitive salary, benefits package (including pension and private medical), visa sponsorship and relocation assistance where required.
Take the next step in your career — contact Caroline Pye today for more details or to apply.
#J-18808-Ljbffr