Cadence Inc
Principal Software Engineer - Low Power Verificastion
Cadence Inc, San Jose, California, United States, 95199
Principal Software Engineer - Low Power Verification (R51413/bz)
We are seeking a highly skilled Senior Software Engineer to join our team in developing next-generation low-power verification software for Palladium and Protium emulation systems. This role focuses on enhancing the debuggability and performance of multi-billion-gate UPF (Unified Power Format) designs in modular compilation 2-state and 4-state flows. Responsibilities
Develop and optimize low-power verification software for Palladium and Protium platforms. Improve UPF design debuggability in IXCOM Modular Compiler and Parallel Partition Compiler (2-state and 4-state flows). Enhance compiled streaming probes and accelerate waveform generation for large-scale designs. Collaborate with R&D, Product Engineering (PE), and Application Engineering (AE) teams to deploy UPF solutions across various flows: AVIP + UPF + 2/4-state UVMA + UPF + 2/4-state MC + UPF Consolidate UPF software across Palladium and Protium platforms. Support key initiatives such as: MC+PPC flow with UPF 4-state Compilation time optimization for UPF Full Vision UPF probe integration SAGE UPF debug with Verisium Qualifications
Bachelors degree in Computer Science or Electrical Engineering with a minimum of 7 years of relevant experience, or Masters degree with 5+ years of experience, or PhD with 1+ year of experience. Required Skills
Strong proficiency in object-oriented design and C++ programming. Experience with standard C/C++ libraries and the C++ Standard Template Library (STL). Proven ability to develop high-performance software for large-scale data processing. Scripting experience in Perl, Tcl/Tk, and/or Python. Familiarity with IEEE 1801 standards and UPF implementation. Experience with Verilog, SystemVerilog, and VHDL. Seniority level
Mid-Senior level Employment type
Full-time Job function
Engineering and Information Technology Industries
Computer Hardware Manufacturing Referrals increase your chances of interviewing at Cadence by 2x Inferred from the description for this job Medical insurance Vision insurance 401(k) Paid maternity leave Paid paternity leave Tuition assistance #J-18808-Ljbffr
We are seeking a highly skilled Senior Software Engineer to join our team in developing next-generation low-power verification software for Palladium and Protium emulation systems. This role focuses on enhancing the debuggability and performance of multi-billion-gate UPF (Unified Power Format) designs in modular compilation 2-state and 4-state flows. Responsibilities
Develop and optimize low-power verification software for Palladium and Protium platforms. Improve UPF design debuggability in IXCOM Modular Compiler and Parallel Partition Compiler (2-state and 4-state flows). Enhance compiled streaming probes and accelerate waveform generation for large-scale designs. Collaborate with R&D, Product Engineering (PE), and Application Engineering (AE) teams to deploy UPF solutions across various flows: AVIP + UPF + 2/4-state UVMA + UPF + 2/4-state MC + UPF Consolidate UPF software across Palladium and Protium platforms. Support key initiatives such as: MC+PPC flow with UPF 4-state Compilation time optimization for UPF Full Vision UPF probe integration SAGE UPF debug with Verisium Qualifications
Bachelors degree in Computer Science or Electrical Engineering with a minimum of 7 years of relevant experience, or Masters degree with 5+ years of experience, or PhD with 1+ year of experience. Required Skills
Strong proficiency in object-oriented design and C++ programming. Experience with standard C/C++ libraries and the C++ Standard Template Library (STL). Proven ability to develop high-performance software for large-scale data processing. Scripting experience in Perl, Tcl/Tk, and/or Python. Familiarity with IEEE 1801 standards and UPF implementation. Experience with Verilog, SystemVerilog, and VHDL. Seniority level
Mid-Senior level Employment type
Full-time Job function
Engineering and Information Technology Industries
Computer Hardware Manufacturing Referrals increase your chances of interviewing at Cadence by 2x Inferred from the description for this job Medical insurance Vision insurance 401(k) Paid maternity leave Paid paternity leave Tuition assistance #J-18808-Ljbffr