Hudson Manpower
Key Responsibilities
Pre-layout STA for feasibility and timing constraint validation Chip/block-level floorplanning and pin assignment Clock spec review and clock tree synthesis Placement, routing, and timing optimization Sign-off tasks: RC extraction, STA, IR-drop analysis, and physical verification Customer meetings and technical presentations Qualifications
BSEE with 5+ years experience; MSEE preferred Strong experience in ASIC physical design and SoC development (28nm/16nm) Proficient in ICC2/Innovus, scripting (Perl/Tcl/Python) Knowledge of frontend design and hierarchical layouts Familiar with power/IR-drop tools (PrimePower/Redhawk) and STA (PrimeTime) Skilled in PV tools and debugging PV errors Excellent communication and problem-solving skills
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Pre-layout STA for feasibility and timing constraint validation Chip/block-level floorplanning and pin assignment Clock spec review and clock tree synthesis Placement, routing, and timing optimization Sign-off tasks: RC extraction, STA, IR-drop analysis, and physical verification Customer meetings and technical presentations Qualifications
BSEE with 5+ years experience; MSEE preferred Strong experience in ASIC physical design and SoC development (28nm/16nm) Proficient in ICC2/Innovus, scripting (Perl/Tcl/Python) Knowledge of frontend design and hierarchical layouts Familiar with power/IR-drop tools (PrimePower/Redhawk) and STA (PrimeTime) Skilled in PV tools and debugging PV errors Excellent communication and problem-solving skills
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