Service Global
Silicon Physical Design Engineer III
Service Global, Burlingame, California, United States, 94012
Iron Systems is an innovative, customer-focused provider of custom-built computing infrastructure platforms such as network servers, storage, OEM/ODM appliances & embedded systems. For more than 15 years, customer have trusted us for our innovative problem solving combined with holistic design, engineering, manufacturing, logistic and global support services.
Job Title: Silicon Physical Design Engineer III Location: US - CA - Burlingame
Skills: Strong understanding in the RTL2GDSII flow and design tapeouts in 16nm/14nm or below process technologies Experience with low power implementation, power gating, multiple voltage rails, strong UPF/CPF knowledge. Experience working with most EDA tools like DC/Genus, ICC2/Innovus, Primetime, PTPX, Primepower Duties:
Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes. Resolve design and flow issues related to physical design, identify potential solutions, and drive execution Power analysis based on netlist
Must Have:
5 years of relevant physical design experience Experience in running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions. Experience in chip power analysis Experience with custom or regular clock tree synthesis implementation at block level or top level, and clock power reduction techniques. Experience with Python, TCL, Perl programming Wish List/ Nice to Have:
MSEE/CS or equivalent experience Education
Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science Master's Degree preferred but not required
Mandatory Skills
5 years of relevant physical design experience Experience in running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs
Job Title: Silicon Physical Design Engineer III Location: US - CA - Burlingame
Skills: Strong understanding in the RTL2GDSII flow and design tapeouts in 16nm/14nm or below process technologies Experience with low power implementation, power gating, multiple voltage rails, strong UPF/CPF knowledge. Experience working with most EDA tools like DC/Genus, ICC2/Innovus, Primetime, PTPX, Primepower Duties:
Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes. Resolve design and flow issues related to physical design, identify potential solutions, and drive execution Power analysis based on netlist
Must Have:
5 years of relevant physical design experience Experience in running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions. Experience in chip power analysis Experience with custom or regular clock tree synthesis implementation at block level or top level, and clock power reduction techniques. Experience with Python, TCL, Perl programming Wish List/ Nice to Have:
MSEE/CS or equivalent experience Education
Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science Master's Degree preferred but not required
Mandatory Skills
5 years of relevant physical design experience Experience in running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs