Google
Memory System Architect, Silicon
Company:
Google
Location:
Mountain View, CA
Job Type:
Full-time
Base Salary Range (US):
$156,000 - $229,000 + bonus, equity, and benefits
Responsibilities
Explore and evaluate different architecture and design choices for power- and performance-efficient coherent and non-coherent memory systems.
Author hardware architecture specifications for next-generation coherent/non-coherent memory systems.
Analyze performance and power trade-offs.
Collaborate with hardware design, verification, emulation, and validation teams to build and test hardware architectures.
Participate in the development of memory system technology and file related patents.
Minimum Qualifications
Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience in micro-architecture and design of ASIC blocks.
Experience designing and implementing Register-Transfer Level (RTL) for CPU, GPU, Cache, MMU, or coherent fabric blocks.
Experience in micro-architecture/design performance analysis, tools, and simulators.
Preferred Qualifications
Master’s degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture.
Experience building build-time configurable designs.
Knowledge of coherent interconnects, caches, or memory systems.
Knowledge of hardware description languages such as SystemVerilog and Verilog.
Equal Opportunity Employer Google is a proud equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity, or Veteran status. We also consider qualified applicants irrespective of criminal histories, consistent with legal requirements. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
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Location:
Mountain View, CA
Job Type:
Full-time
Base Salary Range (US):
$156,000 - $229,000 + bonus, equity, and benefits
Responsibilities
Explore and evaluate different architecture and design choices for power- and performance-efficient coherent and non-coherent memory systems.
Author hardware architecture specifications for next-generation coherent/non-coherent memory systems.
Analyze performance and power trade-offs.
Collaborate with hardware design, verification, emulation, and validation teams to build and test hardware architectures.
Participate in the development of memory system technology and file related patents.
Minimum Qualifications
Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience in micro-architecture and design of ASIC blocks.
Experience designing and implementing Register-Transfer Level (RTL) for CPU, GPU, Cache, MMU, or coherent fabric blocks.
Experience in micro-architecture/design performance analysis, tools, and simulators.
Preferred Qualifications
Master’s degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture.
Experience building build-time configurable designs.
Knowledge of coherent interconnects, caches, or memory systems.
Knowledge of hardware description languages such as SystemVerilog and Verilog.
Equal Opportunity Employer Google is a proud equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity, or Veteran status. We also consider qualified applicants irrespective of criminal histories, consistent with legal requirements. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
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