Energy Jobline ZR
Role Overview
Senior Digital Design Engineer
– Build next‑gen FPGA systems that power global connectivity. Salary: $150,000 – $180,000 per year.
Key Responsibilities
Design, develop, and verify RTL code (Verilog/SystemVerilog) for real‑time digital signal processing systems.
Implement packet decoders and communication protocol logic (e.g., Bluetooth® Low Energy, ZigBee, LoRa, or custom PHYs).
Integrate high‑speed memory interfaces (DDR/DDR3/DDR4) and serial interfaces (LVDS, SPI, I2C, UART, JESD204, PCIe, Ethernet).
Perform synthesis, timing closure, and resource optimization on FPGA platforms (Xilinx or Intel/Altera).
Collaborate with RF, firmware, and systems engineers to optimize end‑to‑end communication performance.
Conduct system‑level analysis and simulation to ensure signal integrity, throughput, and latency targets are met.
Develop testbenches, verification suites, and automation scripts (Python, Tcl).
Drive system‑level reviews and contribute to architecture decisions across hardware and embedded systems.
Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
5+ years of experience in FPGA design and real‑time signal processing.
Proficiency in Verilog/SystemVerilog, digital communication systems, and DSP fundamentals.
Experience with high‑speed memory and serial communication interfaces.
Strong background in FPGA synthesis, simulation, and performance optimization.
Familiarity with simulation and verification tools (ModelSim, Questa, Vivado, VUnit).
Skilled in scripting and automation (Python, Tcl).
Ability to work independently in a fast‑paced, collaborative engineering environment.
Excellent communication and cross‑functional collaboration skills.
Experience 1. Designing distributed DSP systems across multiple FPGAs or compute nodes.
2. Integration of soft‑core or hard‑core processors (ARM, RISC‑V) and embedded Linux environments (e.g., PetaLinux).
3. Experience with synchronization techniques (preamble detection, timing recovery, frequency offset correction).
4. Familiarity with lab instrumentation for validation and debugging (oscilloscopes, logic analyzers, RF tools).
5. Knowledge of low‑power digital design and space‑grade reliability techniques.
6. Understanding of short‑range RF communication standards such as Bluetooth® Low Energy.
Why Join Us?
Salary: $150 K – $180 K (based on experience).
Comprehensive benefits: Health, Dental, Vision, HSA options.
Unlimited PTO and flexible time off.
Paid parental leave.
Learning & Development stipend.
Wellness support: Monthly health & fitness allowance.
Sabbatical program: Recharge after five years.
Cutting‑Edge hardware: Advanced digital and space‑based communication systems.
Additional perks: Team offsites, company swag, and more.
Apply Easy Apply now by clicking the “Apply Now” button.
Equal Opportunity Employer Jobot is an Equal Opportunity Employer. We provide an inclusive work environment that celebrates all qualified candidates receive consideration for employment without regard to race, color, religion, gender, sexual orientation, age, national origin, disability, veteran status, or genetic information. Jobot also prohibits harassment and complies with all applicable federal, state, and local laws.
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– Build next‑gen FPGA systems that power global connectivity. Salary: $150,000 – $180,000 per year.
Key Responsibilities
Design, develop, and verify RTL code (Verilog/SystemVerilog) for real‑time digital signal processing systems.
Implement packet decoders and communication protocol logic (e.g., Bluetooth® Low Energy, ZigBee, LoRa, or custom PHYs).
Integrate high‑speed memory interfaces (DDR/DDR3/DDR4) and serial interfaces (LVDS, SPI, I2C, UART, JESD204, PCIe, Ethernet).
Perform synthesis, timing closure, and resource optimization on FPGA platforms (Xilinx or Intel/Altera).
Collaborate with RF, firmware, and systems engineers to optimize end‑to‑end communication performance.
Conduct system‑level analysis and simulation to ensure signal integrity, throughput, and latency targets are met.
Develop testbenches, verification suites, and automation scripts (Python, Tcl).
Drive system‑level reviews and contribute to architecture decisions across hardware and embedded systems.
Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
5+ years of experience in FPGA design and real‑time signal processing.
Proficiency in Verilog/SystemVerilog, digital communication systems, and DSP fundamentals.
Experience with high‑speed memory and serial communication interfaces.
Strong background in FPGA synthesis, simulation, and performance optimization.
Familiarity with simulation and verification tools (ModelSim, Questa, Vivado, VUnit).
Skilled in scripting and automation (Python, Tcl).
Ability to work independently in a fast‑paced, collaborative engineering environment.
Excellent communication and cross‑functional collaboration skills.
Experience 1. Designing distributed DSP systems across multiple FPGAs or compute nodes.
2. Integration of soft‑core or hard‑core processors (ARM, RISC‑V) and embedded Linux environments (e.g., PetaLinux).
3. Experience with synchronization techniques (preamble detection, timing recovery, frequency offset correction).
4. Familiarity with lab instrumentation for validation and debugging (oscilloscopes, logic analyzers, RF tools).
5. Knowledge of low‑power digital design and space‑grade reliability techniques.
6. Understanding of short‑range RF communication standards such as Bluetooth® Low Energy.
Why Join Us?
Salary: $150 K – $180 K (based on experience).
Comprehensive benefits: Health, Dental, Vision, HSA options.
Unlimited PTO and flexible time off.
Paid parental leave.
Learning & Development stipend.
Wellness support: Monthly health & fitness allowance.
Sabbatical program: Recharge after five years.
Cutting‑Edge hardware: Advanced digital and space‑based communication systems.
Additional perks: Team offsites, company swag, and more.
Apply Easy Apply now by clicking the “Apply Now” button.
Equal Opportunity Employer Jobot is an Equal Opportunity Employer. We provide an inclusive work environment that celebrates all qualified candidates receive consideration for employment without regard to race, color, religion, gender, sexual orientation, age, national origin, disability, veteran status, or genetic information. Jobot also prohibits harassment and complies with all applicable federal, state, and local laws.
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