Comprehensive Resources Inc.
Signal Integrity (SI) & Power Integrity (PI) Engineer
Comprehensive Resources Inc., San Jose, California, United States, 95199
Signal Integrity (SI) & Power Integrity (PI) Engineer
Onsite San Jose, CA & Chandler, AZ
Experience:
5 Years
Work Mode:
Onsite / Work from Office
Role Overview We are seeking a
Signal Integrity Engineer
to support
high-speed interface development and validation
. You’ll work on cutting-edge technologies such as
LPDDR5X, PCIe Gen7, and UCIe (64G) , collaborating closely with design, package, and PCB teams to ensure top performance.
Responsibilities
Perform
channel modeling, extractions, and eye analysis
for high-speed interfaces.
Conduct
pre- and post-layout simulations
to ensure standard compliance.
Analyze
crosstalk, reflections, jitter, insertion/return loss .
Execute
power integrity extractions and simulations
for high-speed interfaces.
Model and analyze
package/board PDN , define
decoupling strategy , and validate performance.
Collaborate across teams to
optimize SI/PI performance .
Generate
technical reports and recommendations
for design decisions.
Provide
SI/PI design guidelines
aligned with system requirements.
Qualifications
BE/MTech
in
Electronics & Communication
or
Electrical & Electronics .
Strong background in
Signal & Power Integrity .
Hands-on with
SI tools
and
PI extraction/simulation tools
(e.g., PowerSI, SIwave, AEDT, HSPICE, or equivalent).
In-depth knowledge of
DDR, PCIe, UCIe standards
and
PDN design best practices .
Familiar with
JEDEC, LPDDR5/6 , and
PCIe/UCIe
standards.
Excellent
analytical, problem-solving, and communication
skills.
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Onsite San Jose, CA & Chandler, AZ
Experience:
5 Years
Work Mode:
Onsite / Work from Office
Role Overview We are seeking a
Signal Integrity Engineer
to support
high-speed interface development and validation
. You’ll work on cutting-edge technologies such as
LPDDR5X, PCIe Gen7, and UCIe (64G) , collaborating closely with design, package, and PCB teams to ensure top performance.
Responsibilities
Perform
channel modeling, extractions, and eye analysis
for high-speed interfaces.
Conduct
pre- and post-layout simulations
to ensure standard compliance.
Analyze
crosstalk, reflections, jitter, insertion/return loss .
Execute
power integrity extractions and simulations
for high-speed interfaces.
Model and analyze
package/board PDN , define
decoupling strategy , and validate performance.
Collaborate across teams to
optimize SI/PI performance .
Generate
technical reports and recommendations
for design decisions.
Provide
SI/PI design guidelines
aligned with system requirements.
Qualifications
BE/MTech
in
Electronics & Communication
or
Electrical & Electronics .
Strong background in
Signal & Power Integrity .
Hands-on with
SI tools
and
PI extraction/simulation tools
(e.g., PowerSI, SIwave, AEDT, HSPICE, or equivalent).
In-depth knowledge of
DDR, PCIe, UCIe standards
and
PDN design best practices .
Familiar with
JEDEC, LPDDR5/6 , and
PCIe/UCIe
standards.
Excellent
analytical, problem-solving, and communication
skills.
#J-18808-Ljbffr