Staftonic LLC
Packaging Engineer
Location: San Jose, CA
Key Responsibilities
Develop and optimise IC package layouts, including netlist creation, BGA and substrate stack‑up design based on project requirements.
Conduct feasibility studies to determine the most efficient pad layouts, routing strategies, interconnect types and via structures.
Design and validate substrate solutions for RF, digital, high‑speed and mixed‑signal devices.
Ensure signal and power integrity (SI/PI) across high‑speed interfaces such as DDR and SERDES.
Apply strong understanding of HDI substrate technologies, DRC setup and manufacturing design rules to ensure design quality and manufacturability.
Work with advanced packaging technologies such as CoWoS, 2.5D/3D integration, RDL, HBM and embedded passives.
Perform design verification to ensure compliance with electrical, thermal and mechanical requirements.
Collaborate with cross‑functional teams and OSAT partners to ensure packaging designs meet performance, reliability and cost objectives.
Required Qualifications
Bachelor’s degree in Electronics or Electrical Engineering (or related discipline).
4 to 8+ years of hands‑on experience in IC package design and substrate development.
Proficiency in Cadence Allegro Package Designer (APD) or SiP Layout is essential.
Strong understanding of CoWoS, UCIE and HBM technologies.
Experience with wire bond, flip‑chip and advanced substrate design processes.
In‑depth knowledge of design rule checks (DRC), signal routing, die breakout optimisation and substrate stack‑up creation.
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Key Responsibilities
Develop and optimise IC package layouts, including netlist creation, BGA and substrate stack‑up design based on project requirements.
Conduct feasibility studies to determine the most efficient pad layouts, routing strategies, interconnect types and via structures.
Design and validate substrate solutions for RF, digital, high‑speed and mixed‑signal devices.
Ensure signal and power integrity (SI/PI) across high‑speed interfaces such as DDR and SERDES.
Apply strong understanding of HDI substrate technologies, DRC setup and manufacturing design rules to ensure design quality and manufacturability.
Work with advanced packaging technologies such as CoWoS, 2.5D/3D integration, RDL, HBM and embedded passives.
Perform design verification to ensure compliance with electrical, thermal and mechanical requirements.
Collaborate with cross‑functional teams and OSAT partners to ensure packaging designs meet performance, reliability and cost objectives.
Required Qualifications
Bachelor’s degree in Electronics or Electrical Engineering (or related discipline).
4 to 8+ years of hands‑on experience in IC package design and substrate development.
Proficiency in Cadence Allegro Package Designer (APD) or SiP Layout is essential.
Strong understanding of CoWoS, UCIE and HBM technologies.
Experience with wire bond, flip‑chip and advanced substrate design processes.
In‑depth knowledge of design rule checks (DRC), signal routing, die breakout optimisation and substrate stack‑up creation.
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