Piper Companies
Piper Companies
is seeking a
Substrate Layout Designer
to join a fast-growing innovator in AI infrastructure, for an
onsite 4-6 month contract
position in
Saratoga, CA . The
Substrate Layout Designer
will play a critical role in making sure high-performance chips—used in AI, data centers, and advanced computing—can actually be built and work reliably.
Responsibilities of the Substrate Layout Designer include:
Helping to lead the physical layout design of high-density substrates for advanced multi-die packages, including planning bump maps, escape routing, and layer stack-ups.
Collaborate with cross-functional engineering teams (e.g., electrical, mechanical, signal/power integrity) to ensure alignment between chip floorplans, system constraints, and packaging requirements.
Utilize industry-standard design tools to create, validate, and optimize substrate layouts, ensuring compliance with design rules and manufacturability standards.
Conduct design reviews and interface with manufacturing partners to support tape-out, fabrication readiness, and iterative improvements.
Ensure electrical performance and reliability through intelligent routing strategies and adherence to signal and power integrity best practices.
Qualifications for the Substrate Layout Designer include:
8+ years of hands‑on experience in substrate layout design for high‑performance semiconductor packaging, including multi‑die or chiplet‑based architectures.
Proficiency with advanced layout tools, including Allegro Cadence APD and AutoCAD, with a strong understanding of design rule checks (DRC), manufacturability (DFM), and fabrication constraints.
Deep knowledge of substrate technologies such as organic substrates, fine‑pitch bump escape routing, and constrained layer stack‑ups.
Familiarity with signal and power integrity principles, and how physical layout impacts electrical performance in high‑speed, high‑density designs.
Strong collaboration and communication skills, with a proven ability to work across engineering disciplines and with external manufacturing partners.
Compensation for the Substrate Layout Designer:
Salary Range:
$148,000-$168,000/year
Comprehensive Benefits:
Medical, Dental, Vision, sick leave if required by law, and 401K
This job opens for applications on 11/5/25. Applications for this job will be accepted for at least 30 days from the posting date.
Keywords: substrate layout, package substrate, BGA routing, chiplet packaging, multi-die packaging, CoWoS, MCM, organic substrate, bump escape routing, high-density interconnect, Allegro APD, Cadence APD, AutoCAD, signal integrity, power integrity, SI/PI, DRC, DFM, substrate design rules, chip packaging, IC packaging, advanced packaging, floorplanning, routing feasibility, substrate stack-up, OSAT, substrate tape-out, semiconductor packaging, FPGA packaging, CPU packaging, GPU packaging, substrate co-design, high-performance ICs, substrate manufacturability, substrate vendor interface
#LI-MB1 #LI-ONSITE
#J-18808-Ljbffr
is seeking a
Substrate Layout Designer
to join a fast-growing innovator in AI infrastructure, for an
onsite 4-6 month contract
position in
Saratoga, CA . The
Substrate Layout Designer
will play a critical role in making sure high-performance chips—used in AI, data centers, and advanced computing—can actually be built and work reliably.
Responsibilities of the Substrate Layout Designer include:
Helping to lead the physical layout design of high-density substrates for advanced multi-die packages, including planning bump maps, escape routing, and layer stack-ups.
Collaborate with cross-functional engineering teams (e.g., electrical, mechanical, signal/power integrity) to ensure alignment between chip floorplans, system constraints, and packaging requirements.
Utilize industry-standard design tools to create, validate, and optimize substrate layouts, ensuring compliance with design rules and manufacturability standards.
Conduct design reviews and interface with manufacturing partners to support tape-out, fabrication readiness, and iterative improvements.
Ensure electrical performance and reliability through intelligent routing strategies and adherence to signal and power integrity best practices.
Qualifications for the Substrate Layout Designer include:
8+ years of hands‑on experience in substrate layout design for high‑performance semiconductor packaging, including multi‑die or chiplet‑based architectures.
Proficiency with advanced layout tools, including Allegro Cadence APD and AutoCAD, with a strong understanding of design rule checks (DRC), manufacturability (DFM), and fabrication constraints.
Deep knowledge of substrate technologies such as organic substrates, fine‑pitch bump escape routing, and constrained layer stack‑ups.
Familiarity with signal and power integrity principles, and how physical layout impacts electrical performance in high‑speed, high‑density designs.
Strong collaboration and communication skills, with a proven ability to work across engineering disciplines and with external manufacturing partners.
Compensation for the Substrate Layout Designer:
Salary Range:
$148,000-$168,000/year
Comprehensive Benefits:
Medical, Dental, Vision, sick leave if required by law, and 401K
This job opens for applications on 11/5/25. Applications for this job will be accepted for at least 30 days from the posting date.
Keywords: substrate layout, package substrate, BGA routing, chiplet packaging, multi-die packaging, CoWoS, MCM, organic substrate, bump escape routing, high-density interconnect, Allegro APD, Cadence APD, AutoCAD, signal integrity, power integrity, SI/PI, DRC, DFM, substrate design rules, chip packaging, IC packaging, advanced packaging, floorplanning, routing feasibility, substrate stack-up, OSAT, substrate tape-out, semiconductor packaging, FPGA packaging, CPU packaging, GPU packaging, substrate co-design, high-performance ICs, substrate manufacturability, substrate vendor interface
#LI-MB1 #LI-ONSITE
#J-18808-Ljbffr