Qualcomm
Company
Qualcomm Technologies, Inc.
Job Area Engineering Group, Engineering Group > ASICS Engineering
General Summary Qualcomm is one of the fastest growing semiconductor organizations, making high-end chips with the most advanced technologies. To support its growing needs, we have a Custom Solutions Team for design and development (RTL to GDS) of various high-speed and low power IP’s (mini-macros) which are used across different sub-systems in SoC. In this position, you will be an integral part of the team with the opportunity to experience the entire ASIC design flow. This position involves the design and development of best-in-class custom digital IP from RTL to GDS for optimizing SoC Power, Performance and Area (PPA). It includes the IP specification definition, RTL design, architecture and circuit design, physical implementation, verification and sign offs. Candidates with coding and flow support experience are preferred.
Job Responsibilities
Use industry standard and internally developed tools and flows (Cadence, Innovus, HSPICE, Primetime etc) to execute architecture or circuit level design with defined specifications.
Oversee the IP implementation through various design stages: RTL development, Transistor level analysis, Place and Route implementation and Timing closure.
Simulate and sign off design margin and PPA metrics.
Generate and release IP collaterals (functional/DFT/timing models, LEF abstract, DEF, etc) for SoC consumption.
Conduct design reviews and documentation.
Flow and methodology enablement support.
Close collaboration with different teams across various time zones.
Skillset/Experience
Strong background and exposure in one of the digital design areas:
Experience of digital library architecture and circuit design, and simulation sign off (HSPICE), such as custom circuit, standard cell or SRAM.
Experience with transistor level circuit analysis flows: ESPCV, Spice, Monte Carlo simulations, Nanotime.
Experience with synthesis, physical design flows (Genus, Innovus or FusionCompiler) and STA timing closure (PrimeTime or Tempus).
Knowledge of semiconductor device physics and behavior; understanding advanced technology, such as FinFET, Gate All Around is a plus.
Adaptive to non-standard design flow.
Programming skill in python, perl, tcl, shell, skill, etc is a strong plus.
Variation-aware design experience is a plus.
Exposure to RTL, Synthesis, Formal & functional verification or DFT is a plus.
Minimum Qualifications
Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR Master’s degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR PhD in Science, Engineering, or related field.
EEO Employer Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected classification.
Accommodation Statement Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll‑free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).
Pay Range And Other Compensation & Benefits $115,600.00 - $173,400.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits here.
Seniority Level Not Applicable
Employment Type Full-time
Job Function Other
Industries Telecommunications
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Job Area Engineering Group, Engineering Group > ASICS Engineering
General Summary Qualcomm is one of the fastest growing semiconductor organizations, making high-end chips with the most advanced technologies. To support its growing needs, we have a Custom Solutions Team for design and development (RTL to GDS) of various high-speed and low power IP’s (mini-macros) which are used across different sub-systems in SoC. In this position, you will be an integral part of the team with the opportunity to experience the entire ASIC design flow. This position involves the design and development of best-in-class custom digital IP from RTL to GDS for optimizing SoC Power, Performance and Area (PPA). It includes the IP specification definition, RTL design, architecture and circuit design, physical implementation, verification and sign offs. Candidates with coding and flow support experience are preferred.
Job Responsibilities
Use industry standard and internally developed tools and flows (Cadence, Innovus, HSPICE, Primetime etc) to execute architecture or circuit level design with defined specifications.
Oversee the IP implementation through various design stages: RTL development, Transistor level analysis, Place and Route implementation and Timing closure.
Simulate and sign off design margin and PPA metrics.
Generate and release IP collaterals (functional/DFT/timing models, LEF abstract, DEF, etc) for SoC consumption.
Conduct design reviews and documentation.
Flow and methodology enablement support.
Close collaboration with different teams across various time zones.
Skillset/Experience
Strong background and exposure in one of the digital design areas:
Experience of digital library architecture and circuit design, and simulation sign off (HSPICE), such as custom circuit, standard cell or SRAM.
Experience with transistor level circuit analysis flows: ESPCV, Spice, Monte Carlo simulations, Nanotime.
Experience with synthesis, physical design flows (Genus, Innovus or FusionCompiler) and STA timing closure (PrimeTime or Tempus).
Knowledge of semiconductor device physics and behavior; understanding advanced technology, such as FinFET, Gate All Around is a plus.
Adaptive to non-standard design flow.
Programming skill in python, perl, tcl, shell, skill, etc is a strong plus.
Variation-aware design experience is a plus.
Exposure to RTL, Synthesis, Formal & functional verification or DFT is a plus.
Minimum Qualifications
Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR Master’s degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR PhD in Science, Engineering, or related field.
EEO Employer Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected classification.
Accommodation Statement Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll‑free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).
Pay Range And Other Compensation & Benefits $115,600.00 - $173,400.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits here.
Seniority Level Not Applicable
Employment Type Full-time
Job Function Other
Industries Telecommunications
#J-18808-Ljbffr