Qualcomm
Overview
Join to apply for the
Custom IP Design Engineer
role at
Qualcomm . Qualcomm is a leading semiconductor company developing high-end chips and advanced technologies. The Custom Solutions Team is responsible for design and development (RTL to GDS) of various high-speed and low-power IPs (mini-macros) used across SoC sub-systems. This role provides exposure to the entire ASIC design flow with the opportunity to design and develop best-in-class custom digital IP from RTL to GDS for optimizing SoC Power, Performance and Area (PPA). Responsibilities include IP specification definition, RTL design, architecture and circuit design, physical implementation, verification and sign-off. Candidates with coding and flow support experience are preferred.
Responsibilities
Use industry-standard and internally developed tools and flows (Cadence, Innovus, HSPICE, Primetime, etc.) to execute architecture or circuit-level design with defined specifications.
Oversee the IP implementation through design stages: RTL development, transistor-level analysis, Place and Route implementation and Timing closure.
Simulate and sign off design margin and PPA metrics.
Generate and release IP collaterals (functional/DFT/timing models, LEF abstract, DEF, etc.) for SoC consumption.
Conduct design reviews and documentation.
Flow and methodology enablement support.
Coordinate closely with different teams across various time zones.
Skillset / Experience
Strong background in one of the digital design areas, including:
Digital library architecture and circuit design, and simulation sign-off (HSPICE), such as custom circuit, standard cell or SRAM.
Transistor-level circuit analysis flows: ESPCV, Spice, Monte Carlo simulations, Nanotime.
Synthesis, physical design flows (Genus, Innovus or FusionCompiler) and STA timing closure (PrimeTime or Tempus).
Knowledge of semiconductor device physics and behavior; understanding advanced technology such as FinFET or Gate All Around is a plus.
Adaptive to non-standard design flows.
Programming skills in Python, Perl, Tcl, Shell; other scripting is a strong plus.
Variation-aware design experience is a plus.
Exposure to RTL, Synthesis, Formal & functional verification or DFT is a plus.
Minimum Qualifications
Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR Master’s degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR PhD in Science, Engineering, or related field.
Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Qualcomm will provide reasonable accommodations to support individuals with disabilities to participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities.
EEO and Policies EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects employees to abide by all applicable policies and procedures, including security and protection of confidential information.
Pay Range and Benefits $115,600.00 - $173,400.00
The pay scale reflects the broad range for this job code and location. Salary is one component of total compensation at Qualcomm, which also includes a competitive annual discretionary bonus program and potential RSU grants. Details about US benefits can be discussed with the recruiter.
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Join to apply for the
Custom IP Design Engineer
role at
Qualcomm . Qualcomm is a leading semiconductor company developing high-end chips and advanced technologies. The Custom Solutions Team is responsible for design and development (RTL to GDS) of various high-speed and low-power IPs (mini-macros) used across SoC sub-systems. This role provides exposure to the entire ASIC design flow with the opportunity to design and develop best-in-class custom digital IP from RTL to GDS for optimizing SoC Power, Performance and Area (PPA). Responsibilities include IP specification definition, RTL design, architecture and circuit design, physical implementation, verification and sign-off. Candidates with coding and flow support experience are preferred.
Responsibilities
Use industry-standard and internally developed tools and flows (Cadence, Innovus, HSPICE, Primetime, etc.) to execute architecture or circuit-level design with defined specifications.
Oversee the IP implementation through design stages: RTL development, transistor-level analysis, Place and Route implementation and Timing closure.
Simulate and sign off design margin and PPA metrics.
Generate and release IP collaterals (functional/DFT/timing models, LEF abstract, DEF, etc.) for SoC consumption.
Conduct design reviews and documentation.
Flow and methodology enablement support.
Coordinate closely with different teams across various time zones.
Skillset / Experience
Strong background in one of the digital design areas, including:
Digital library architecture and circuit design, and simulation sign-off (HSPICE), such as custom circuit, standard cell or SRAM.
Transistor-level circuit analysis flows: ESPCV, Spice, Monte Carlo simulations, Nanotime.
Synthesis, physical design flows (Genus, Innovus or FusionCompiler) and STA timing closure (PrimeTime or Tempus).
Knowledge of semiconductor device physics and behavior; understanding advanced technology such as FinFET or Gate All Around is a plus.
Adaptive to non-standard design flows.
Programming skills in Python, Perl, Tcl, Shell; other scripting is a strong plus.
Variation-aware design experience is a plus.
Exposure to RTL, Synthesis, Formal & functional verification or DFT is a plus.
Minimum Qualifications
Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR Master’s degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR PhD in Science, Engineering, or related field.
Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Qualcomm will provide reasonable accommodations to support individuals with disabilities to participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities.
EEO and Policies EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects employees to abide by all applicable policies and procedures, including security and protection of confidential information.
Pay Range and Benefits $115,600.00 - $173,400.00
The pay scale reflects the broad range for this job code and location. Salary is one component of total compensation at Qualcomm, which also includes a competitive annual discretionary bonus program and potential RSU grants. Details about US benefits can be discussed with the recruiter.
#J-18808-Ljbffr