Nokia
In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. The
Network Infrastructure
group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise
Join
Optical Networks division , where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we’ve united two industry leaders to create an optical networking powerhouse—combining cutting-edge technology with proven leadership to redefine the future of connectivity.
The successful candidate shall possess abundant experience in designing complex DSP for communication systems. She/he shall also have decent knowledge in analog/mixed-signal circuitry to perform the modeling and optimization of the overall high-performance front ends for communication SoCs.
Qualifications
Mandatory Knowledge/Skills/Abilities:
Have prominent tracking record in modeling analog/mixed-signal IPs, including but limited to SERDES, optical links, and wireless transmission systems.
Hands‑on in modeling and simulating with System‑Verilog (WREAL), Verilog-AMS, and/or C, C++.
Have a decent understanding in CMOS analog / mixed-signal design.
Preferred Knowledge/Skill/Abilities:
Able to create IBIS-AMI model.
Can code in System-Verilog (WREAL).
Able perform .LIB generation
Fluent in verbal and written communications;
Independently resolves issues and conquer design challenges;
Self‑motivated and detail‑oriented;
Has the knowledge of (optical) communication theories and Matlab coding.
Education and Experience Requirements:
Principal Design Engineer: M.S. in E.E. with 12+ years’ experience, or Ph.D. in E.E. with 8+ years’ experience
Responsibilities
Model the circuit blocks and mixed‑signal IPs, including but not limited to high‑speed ADCs, DACs, CTLE, FFE, and PLLs, to work with the architect and designers to achieve the optimal system‑level performance.
Perform the functional verification and timing analysis on the IPs and the blocks.
Work with the digital verification team to generate an adequate interface to ensure the robustness of the design.
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Network Infrastructure
group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise
Join
Optical Networks division , where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we’ve united two industry leaders to create an optical networking powerhouse—combining cutting-edge technology with proven leadership to redefine the future of connectivity.
The successful candidate shall possess abundant experience in designing complex DSP for communication systems. She/he shall also have decent knowledge in analog/mixed-signal circuitry to perform the modeling and optimization of the overall high-performance front ends for communication SoCs.
Qualifications
Mandatory Knowledge/Skills/Abilities:
Have prominent tracking record in modeling analog/mixed-signal IPs, including but limited to SERDES, optical links, and wireless transmission systems.
Hands‑on in modeling and simulating with System‑Verilog (WREAL), Verilog-AMS, and/or C, C++.
Have a decent understanding in CMOS analog / mixed-signal design.
Preferred Knowledge/Skill/Abilities:
Able to create IBIS-AMI model.
Can code in System-Verilog (WREAL).
Able perform .LIB generation
Fluent in verbal and written communications;
Independently resolves issues and conquer design challenges;
Self‑motivated and detail‑oriented;
Has the knowledge of (optical) communication theories and Matlab coding.
Education and Experience Requirements:
Principal Design Engineer: M.S. in E.E. with 12+ years’ experience, or Ph.D. in E.E. with 8+ years’ experience
Responsibilities
Model the circuit blocks and mixed‑signal IPs, including but not limited to high‑speed ADCs, DACs, CTLE, FFE, and PLLs, to work with the architect and designers to achieve the optimal system‑level performance.
Perform the functional verification and timing analysis on the IPs and the blocks.
Work with the digital verification team to generate an adequate interface to ensure the robustness of the design.
#J-18808-Ljbffr