Nhanced Semi
As a Senior Physical Design Engineer, you will be responsible for the physical implementation of complex ASIC and interposer designs, from floorplanning to tapeout. You will work in a highly collaborative environment, leveraging Cadence design tools and Git for version control, ensuring efficient and high-quality execution. The ideal candidate is a self-starter who thrives with minimal supervision and has a strong background in advanced node physical design methodologies.
Responsibilities
Drive
full-chip physical implementation
of 2.5D interposer and ASIC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization. Ensure design compliance with
timing, power, and area (PPA) requirements , as well as DFM, DRC, and LVS constraints. Utilize
Cadence tools
(Innovus, Virtuoso, Tempus, Voltus, Pegasus, etc.) for physical design, verification, and signoff. Develop and execute
timing closure strategies , working with STA engineers to meet performance goals. Optimize power
distribution networks (PDN)
and
electromigration (EM) reliability
in multi-die packaging environments. Work with
package and system engineers
to optimize die-to-die interconnect, bump placement, and TSV integration. Collaborate with
RTL designers, DFT engineers, and backend teams
to ensure seamless integration. Implement
ECOs (Engineering Change Orders)
and efficiently iterate design revisions. Utilize
Git-based version control workflows
for design database management and collaborative development. Identify and resolve
congestion, signal integrity (SI), and crosstalk
issues in complex designs. Ensure
successful tapeout
by running full-chip physical verification and working with foundry partners. Qualifications Required: 5+ years of experience
in physical design, specifically in
ASIC, SoC, or advanced packaging (2.5D, 3DIC)
technologies. Hands-on experience with
Git-based version control systems
for managing design revisions. Experience with
timing closure and signal integrity . Preferred: Experience in
2.5D/3DIC packaging
and heterogeneous integration. Hands-on experience with
chip-package co-design
methodologies. Prior engagement with
foundry process nodes and PDKs
for advanced packaging. Skills Required: Proficiency in
Cadence tools
for physical design, timing analysis, and signoff. Strong understanding of
RTL-to-GDSII flows , including floorplanning, power planning, place-and-route, and timing closure. Working knowledge of
parasitic extraction (PEX), power integrity (PI), and thermal analysis
in multi-die environments. Ability to
work independently
with minimal supervision and drive tasks to completion. Excellent verbal and written
communication skills
for collaboration across engineering teams. Strong
debugging skills
and ability to analyze tool reports, logs, and simulation results. Preferred: Familiarity with
high-speed die-to-die interconnect design and CoWoS/Fanout-WLP processes . Knowledge of
scripting (TCL, Python, Perl, or shell scripting)
to automate design tasks. Job Location More Information For company description, benefits package, and application instructions see the Careers Page
. Phone: +1 331-701-7070 Fax: +1 331-701-7055
#J-18808-Ljbffr
full-chip physical implementation
of 2.5D interposer and ASIC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization. Ensure design compliance with
timing, power, and area (PPA) requirements , as well as DFM, DRC, and LVS constraints. Utilize
Cadence tools
(Innovus, Virtuoso, Tempus, Voltus, Pegasus, etc.) for physical design, verification, and signoff. Develop and execute
timing closure strategies , working with STA engineers to meet performance goals. Optimize power
distribution networks (PDN)
and
electromigration (EM) reliability
in multi-die packaging environments. Work with
package and system engineers
to optimize die-to-die interconnect, bump placement, and TSV integration. Collaborate with
RTL designers, DFT engineers, and backend teams
to ensure seamless integration. Implement
ECOs (Engineering Change Orders)
and efficiently iterate design revisions. Utilize
Git-based version control workflows
for design database management and collaborative development. Identify and resolve
congestion, signal integrity (SI), and crosstalk
issues in complex designs. Ensure
successful tapeout
by running full-chip physical verification and working with foundry partners. Qualifications Required: 5+ years of experience
in physical design, specifically in
ASIC, SoC, or advanced packaging (2.5D, 3DIC)
technologies. Hands-on experience with
Git-based version control systems
for managing design revisions. Experience with
timing closure and signal integrity . Preferred: Experience in
2.5D/3DIC packaging
and heterogeneous integration. Hands-on experience with
chip-package co-design
methodologies. Prior engagement with
foundry process nodes and PDKs
for advanced packaging. Skills Required: Proficiency in
Cadence tools
for physical design, timing analysis, and signoff. Strong understanding of
RTL-to-GDSII flows , including floorplanning, power planning, place-and-route, and timing closure. Working knowledge of
parasitic extraction (PEX), power integrity (PI), and thermal analysis
in multi-die environments. Ability to
work independently
with minimal supervision and drive tasks to completion. Excellent verbal and written
communication skills
for collaboration across engineering teams. Strong
debugging skills
and ability to analyze tool reports, logs, and simulation results. Preferred: Familiarity with
high-speed die-to-die interconnect design and CoWoS/Fanout-WLP processes . Knowledge of
scripting (TCL, Python, Perl, or shell scripting)
to automate design tasks. Job Location More Information For company description, benefits package, and application instructions see the Careers Page
. Phone: +1 331-701-7070 Fax: +1 331-701-7055
#J-18808-Ljbffr