Pure Storage
THE ROLE
You will lead the Signal and Power Integrity (SI/PI) strategy for our next-generation, high-performance storage platforms, ensuring system-level electrical robustness. You will own the end-to-end electrical architecture—from high-level concept definition and advanced modeling to final lab validation and compliance sign-off. This critical role involves acting as a technical leader and cross-functional facilitator, collaborating with Hardware Design, PCB Layout, and firmware teams to ship robust, cutting-edge products globally.
WHAT YOU'LL DO
Architect and own the SI strategy
for all cutting-edge, high-speed interfaces (e.g., PCIe Gen5+, 800G Ethernet, DDR5), ensuring product reliability and maximizing performance margins from initial link budgets through production release.
Drive Power Integrity (PI) excellence
by establishing and validating robust Power Delivery Network (PDN) targets, including impedance profiling, decoupling optimization, and mitigating SSN for complex, high-current draw hardware designs.
Define and enforce global design standards
by collaborating with PCB layout and mechanical teams on stackups, materials, routing rules, and constraints to achieve first-pass silicon success and manufacturing quality across product lines.
Serve as the SI/PI technical lead
for complex system-level debug, root-cause analysis, and corrective action implementation to resolve critical issues across prototypes, validation, and field escalations.
Elevate engineering efficiency
by developing and standardizing automated simulation flows, reporting pipelines (using Python or MATLAB), and Continuous Integration (CI) style checks for and layout quality across the hardware organization.
WHAT YOU BRING
Expert-level proficiency in high-speed channel design and validation
for modern interfaces like PCIe Gen4+, 25G+ SerDes Ethernet, and DDR4/DDR5, including deep knowledge of EM theory, crosstalk mitigation, and jitter analysis.
Mastery of industry-standard EDA tools
(e.g., Sigrity, ADS, HFSS, HyperLynx) for pre- and post-layout SI/PI analysis (IBIS-AMI, COM, and channel modeling) and hands‑on lab validation using high-speed instruments (VNA, TDR, BERT, Oscilloscopes).
Advanced Power Integrity design experience
in target impedance methodology, VRM modeling, noise coupling analysis, and defining component placement strategies to mitigate SSN and ground bounce.
Demonstrated ability to lead technical initiatives
and drive complex cross-functional decisions, acting as a facilitator and mentor to junior engineers while documenting best practices to champion "quality by design."
Fluency in developing scripts
(e.g., Python, MATLAB) for automating SI/PI model extraction, simulation workflows, post-processing, and generating standardized reports.
We are primarily an in‑office environment and therefore, you will be expected to work from the Santa Clara, CA office in compliance with Pure’s policies, unless you are on PTO, or work travel, or other approved leave.
#LI-ONSITE
Salary ranges are determined based on role, level and location. For positions open to candidates in multiple geographical locations, the base salary range is reflective of the labor market across the applicable locations.
This role may be eligible for incentive pay and/or equity.
There is no application deadline and we accept applications on an ongoing basis until the job is filled.
The annual base salary range is: $175,000 — $263,000 USD
WHAT YOU CAN EXPECT FROM US:
Pure Innovation : We celebrate those who think critically, like a challenge and aspire to be trailblazers.
Pure Growth : We give you the space and support to grow along with us and to contribute to something meaningful. We have been Named Fortune's Best Large Workplaces in the Bay Area™, Fortune's Best Workplaces for Millennials™ and certified as a Great Place to Work®!
Pure Team : We build each other up and set aside ego for the greater good.
And because we understand the value of bringing your full and best self to work, we offer a variety of perks to manage a healthy balance, including flexible time off, wellness resources and company-sponsored team events. Check out purebenefits.com for more information.
ACCOMMODATIONS AND ACCESSIBILITY: Candidates with disabilities may request accommodations for all aspects of our hiring process. For more on this, contact us at TA-Ops@purestorage.com if you’re invited to an interview.
OUR COMMITMENT TO A STRONG AND INCLUSIVE TEAM: We’re forging a future where everyone finds their rightful place and where every voice matters. Where uniqueness isn’t just accepted but embraced. That’s why we are committed to fostering the growth and development of every person, cultivating a sense of community through our Employee Resource Groups and advocating for inclusive leadership. Pure is proud to be an equal opportunity and affirmative action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or any other characteristic legally protected by the laws of the jurisdiction in which you are being considered for hire.
JOIN US AND BRING YOUR BEST.
BRING YOUR BOLD.
BRING YOUR FLASH.
#J-18808-Ljbffr
WHAT YOU'LL DO
Architect and own the SI strategy
for all cutting-edge, high-speed interfaces (e.g., PCIe Gen5+, 800G Ethernet, DDR5), ensuring product reliability and maximizing performance margins from initial link budgets through production release.
Drive Power Integrity (PI) excellence
by establishing and validating robust Power Delivery Network (PDN) targets, including impedance profiling, decoupling optimization, and mitigating SSN for complex, high-current draw hardware designs.
Define and enforce global design standards
by collaborating with PCB layout and mechanical teams on stackups, materials, routing rules, and constraints to achieve first-pass silicon success and manufacturing quality across product lines.
Serve as the SI/PI technical lead
for complex system-level debug, root-cause analysis, and corrective action implementation to resolve critical issues across prototypes, validation, and field escalations.
Elevate engineering efficiency
by developing and standardizing automated simulation flows, reporting pipelines (using Python or MATLAB), and Continuous Integration (CI) style checks for and layout quality across the hardware organization.
WHAT YOU BRING
Expert-level proficiency in high-speed channel design and validation
for modern interfaces like PCIe Gen4+, 25G+ SerDes Ethernet, and DDR4/DDR5, including deep knowledge of EM theory, crosstalk mitigation, and jitter analysis.
Mastery of industry-standard EDA tools
(e.g., Sigrity, ADS, HFSS, HyperLynx) for pre- and post-layout SI/PI analysis (IBIS-AMI, COM, and channel modeling) and hands‑on lab validation using high-speed instruments (VNA, TDR, BERT, Oscilloscopes).
Advanced Power Integrity design experience
in target impedance methodology, VRM modeling, noise coupling analysis, and defining component placement strategies to mitigate SSN and ground bounce.
Demonstrated ability to lead technical initiatives
and drive complex cross-functional decisions, acting as a facilitator and mentor to junior engineers while documenting best practices to champion "quality by design."
Fluency in developing scripts
(e.g., Python, MATLAB) for automating SI/PI model extraction, simulation workflows, post-processing, and generating standardized reports.
We are primarily an in‑office environment and therefore, you will be expected to work from the Santa Clara, CA office in compliance with Pure’s policies, unless you are on PTO, or work travel, or other approved leave.
#LI-ONSITE
Salary ranges are determined based on role, level and location. For positions open to candidates in multiple geographical locations, the base salary range is reflective of the labor market across the applicable locations.
This role may be eligible for incentive pay and/or equity.
There is no application deadline and we accept applications on an ongoing basis until the job is filled.
The annual base salary range is: $175,000 — $263,000 USD
WHAT YOU CAN EXPECT FROM US:
Pure Innovation : We celebrate those who think critically, like a challenge and aspire to be trailblazers.
Pure Growth : We give you the space and support to grow along with us and to contribute to something meaningful. We have been Named Fortune's Best Large Workplaces in the Bay Area™, Fortune's Best Workplaces for Millennials™ and certified as a Great Place to Work®!
Pure Team : We build each other up and set aside ego for the greater good.
And because we understand the value of bringing your full and best self to work, we offer a variety of perks to manage a healthy balance, including flexible time off, wellness resources and company-sponsored team events. Check out purebenefits.com for more information.
ACCOMMODATIONS AND ACCESSIBILITY: Candidates with disabilities may request accommodations for all aspects of our hiring process. For more on this, contact us at TA-Ops@purestorage.com if you’re invited to an interview.
OUR COMMITMENT TO A STRONG AND INCLUSIVE TEAM: We’re forging a future where everyone finds their rightful place and where every voice matters. Where uniqueness isn’t just accepted but embraced. That’s why we are committed to fostering the growth and development of every person, cultivating a sense of community through our Employee Resource Groups and advocating for inclusive leadership. Pure is proud to be an equal opportunity and affirmative action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or any other characteristic legally protected by the laws of the jurisdiction in which you are being considered for hire.
JOIN US AND BRING YOUR BEST.
BRING YOUR BOLD.
BRING YOUR FLASH.
#J-18808-Ljbffr