Capgemini Engineering
SoC/ ASIC Verification Engineer- Semiconductor
Capgemini Engineering, Boston, Massachusetts, us, 02298
SoC Verification Architect
About the Company
Join Capgemini's team as a SoC Verification Architect, where you'll play a critical role in verifying cutting‑edge System‑on‑Chip designs for next‑generation products. You'll architect and implement advanced verification environments, ensuring the highest quality and reliability in complex digital systems.
About the Role
Architect and develop a complete functional verification including testbenches reference models, and monitors/drivers.
Responsibilities
Define and execute comprehensive verification test plans using constrained random, directed testing, and coverage analysis.
Implement testbenches using UVM, SystemVerilog, C/C++, and DPI.
Verify designs across multiple hierarchy levels: block/unit, subsystem, and SoC.
Collaborate closely with the logic designers to debug failures and resolve design issues.
Qualifications
Bachelors of Science in Electrical Engineering, Computer Engineering or related field.
Required Skills
5+ years' experience in Design Verification.
Methodology expertise in UVM and SystemVerilog for SoC verification with the ability to create hierarchical, reusable, and scalable testbench architectures.
Strong background in Object‑Oriented Programming (OOP) with SystemVerilog.
Hands‑on experience with EA verification/debugging tools and revision control systems.
Proficiency in Python or Shell scripting.
Technical Domains: Ethernet or Mixed‑Signal Design Verification, Arm‑based SoC Verification.
Equal Opportunity Statement Capgemini is committed to diversity and inclusivity.
Seniority level Mid‑Senior level
Employment type Full‑time
Job function Other, Design, and Writing/Editing
Industries Semiconductor Manufacturing
Benefits
Medical insurance
Vision insurance
401(k)
Disability insurance
#J-18808-Ljbffr
Join Capgemini's team as a SoC Verification Architect, where you'll play a critical role in verifying cutting‑edge System‑on‑Chip designs for next‑generation products. You'll architect and implement advanced verification environments, ensuring the highest quality and reliability in complex digital systems.
About the Role
Architect and develop a complete functional verification including testbenches reference models, and monitors/drivers.
Responsibilities
Define and execute comprehensive verification test plans using constrained random, directed testing, and coverage analysis.
Implement testbenches using UVM, SystemVerilog, C/C++, and DPI.
Verify designs across multiple hierarchy levels: block/unit, subsystem, and SoC.
Collaborate closely with the logic designers to debug failures and resolve design issues.
Qualifications
Bachelors of Science in Electrical Engineering, Computer Engineering or related field.
Required Skills
5+ years' experience in Design Verification.
Methodology expertise in UVM and SystemVerilog for SoC verification with the ability to create hierarchical, reusable, and scalable testbench architectures.
Strong background in Object‑Oriented Programming (OOP) with SystemVerilog.
Hands‑on experience with EA verification/debugging tools and revision control systems.
Proficiency in Python or Shell scripting.
Technical Domains: Ethernet or Mixed‑Signal Design Verification, Arm‑based SoC Verification.
Equal Opportunity Statement Capgemini is committed to diversity and inclusivity.
Seniority level Mid‑Senior level
Employment type Full‑time
Job function Other, Design, and Writing/Editing
Industries Semiconductor Manufacturing
Benefits
Medical insurance
Vision insurance
401(k)
Disability insurance
#J-18808-Ljbffr