Capgemini
About the Job You’re Considering
We’re seeking a
Design Verification Engineer
for a
hybrid role
based in
Santa Clara, CA
or
Boston, MA . This position focuses on
Functional Verification
and offers an opportunity to work on cutting‑edge SoC designs in a collaborative environment.
Your Role
Architect and develop a complete functional verification environment, including testbench, reference models, and monitors/drivers.
Define comprehensive verification test plans using constrained random, directed testing, and coverage analysis.
Implement testbenches using UVM, SystemVerilog, C/C++, and DPI.
Verify designs across multiple hierarchy levels: block/unit, subsystem, and SoC.
Collaborate closely with logic designers to debug failures and resolve design issues.
Your Skills and Experience
Education/Experience:
BS/MS degree with 5–12 years of relevant professional experience.
Methodology:
Expertise in UVM and SystemVerilog for SoC verification, including creating test plans and designing hierarchical, reusable, and scalable testbench architectures.
Programming:
Strong background in Object‑Oriented Programming (OOP) with SystemVerilog and constrained random techniques.
Tools:
Hands‑on experience with EDA verification/debugging tools and revision control systems.
Scripting:
Proficiency in Python or Shell scripting.
Technical Domains:
Experience in one or more areas—Ethernet, Mixed Signal Digital design verification, Formal Property Verification (Jasper or similar tools), or ARM‑based SoC verification.
Benefits (Life at Capgemini)
Flexible work
Healthcare including dental, vision, mental health, and well‑being programs
Financial well‑being programs such as 401(k) and Employee Share Ownership Plan
Paid time off and paid holidays
Paid parental leave
Family building benefits like adoption assistance, surrogacy, and cryopreservation
Social well‑being benefits like subsidized back‑up child/elder care and tutoring
Mentoring, coaching and learning programs
Employee Resource Groups
Disaster Relief
Salary Range Capgemini discloses salary range information in compliance with state and local pay transparency obligations. The disclosed range represents the lowest to highest salary we, in good faith, believe we would pay for this role at the time of this posting, although we may ultimately pay more or less than the disclosed range, and the range may be modified in the future. At Capgemini, it is not typical for an individual to be hired at or near the top of the range for their role. The base salary range for the tagged location is
[$97,700 - $182,624 / year] . This role may be eligible for other compensation including variable compensation, bonus, or commission. Full-time regular employees are eligible for paid time off, medical/dental/vision insurance, 401(k), and any other benefits to eligible employees.
Applicants for employment in the US must have valid work authorization that does not now and/or will not in the future require sponsorship of a visa for employment authorization in the US by Capgemini.
Capgemini is an Equal Opportunity Employer encouraging inclusion in the workplace. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law.
Capgemini is committed to providing reasonable accommodations during our recruitment process. If you need assistance or accommodation, please reach out to your recruiting contact.
When you join Capgemini, you don’t just start a new job. You become part of something bigger.
#J-18808-Ljbffr
Design Verification Engineer
for a
hybrid role
based in
Santa Clara, CA
or
Boston, MA . This position focuses on
Functional Verification
and offers an opportunity to work on cutting‑edge SoC designs in a collaborative environment.
Your Role
Architect and develop a complete functional verification environment, including testbench, reference models, and monitors/drivers.
Define comprehensive verification test plans using constrained random, directed testing, and coverage analysis.
Implement testbenches using UVM, SystemVerilog, C/C++, and DPI.
Verify designs across multiple hierarchy levels: block/unit, subsystem, and SoC.
Collaborate closely with logic designers to debug failures and resolve design issues.
Your Skills and Experience
Education/Experience:
BS/MS degree with 5–12 years of relevant professional experience.
Methodology:
Expertise in UVM and SystemVerilog for SoC verification, including creating test plans and designing hierarchical, reusable, and scalable testbench architectures.
Programming:
Strong background in Object‑Oriented Programming (OOP) with SystemVerilog and constrained random techniques.
Tools:
Hands‑on experience with EDA verification/debugging tools and revision control systems.
Scripting:
Proficiency in Python or Shell scripting.
Technical Domains:
Experience in one or more areas—Ethernet, Mixed Signal Digital design verification, Formal Property Verification (Jasper or similar tools), or ARM‑based SoC verification.
Benefits (Life at Capgemini)
Flexible work
Healthcare including dental, vision, mental health, and well‑being programs
Financial well‑being programs such as 401(k) and Employee Share Ownership Plan
Paid time off and paid holidays
Paid parental leave
Family building benefits like adoption assistance, surrogacy, and cryopreservation
Social well‑being benefits like subsidized back‑up child/elder care and tutoring
Mentoring, coaching and learning programs
Employee Resource Groups
Disaster Relief
Salary Range Capgemini discloses salary range information in compliance with state and local pay transparency obligations. The disclosed range represents the lowest to highest salary we, in good faith, believe we would pay for this role at the time of this posting, although we may ultimately pay more or less than the disclosed range, and the range may be modified in the future. At Capgemini, it is not typical for an individual to be hired at or near the top of the range for their role. The base salary range for the tagged location is
[$97,700 - $182,624 / year] . This role may be eligible for other compensation including variable compensation, bonus, or commission. Full-time regular employees are eligible for paid time off, medical/dental/vision insurance, 401(k), and any other benefits to eligible employees.
Applicants for employment in the US must have valid work authorization that does not now and/or will not in the future require sponsorship of a visa for employment authorization in the US by Capgemini.
Capgemini is an Equal Opportunity Employer encouraging inclusion in the workplace. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law.
Capgemini is committed to providing reasonable accommodations during our recruitment process. If you need assistance or accommodation, please reach out to your recruiting contact.
When you join Capgemini, you don’t just start a new job. You become part of something bigger.
#J-18808-Ljbffr