Ursus
JOB TITLE: ASIC Power Engineer
LOCATION: Sunnyvale, CA (Hybrid)
DURATION: 1/8/2026 - 7/7/2026
PAY RANGE: $109-$119/hr.
TOP 3 SKILLS:
Experience with Synopsys (DC, ICC, PTPX/Prime Power, VCS, Verdi) and/or Cadence (Joules)
Should know how to use Python, Perl (or similar) scripting, and data-post-processing tools
Experience in low power design, tools, and methodologies, including power intent UPF specifications, Silicon Power Characterization
COMPANY:
Our client is a Fortune 500 multi-national technology company headquartered in Menlo Park, CA.
DUTIES:
The ASIC Power Engineer will perform power analysis and optimizations in ASIC for AR/VR products. Areas of interest include Machine Learning. Primary languages are Python, Tcl, and SystemVerilog.
RESPONSIBILITIES:
Perform PPA optimization with Fusion Compiler
Conduct RTL and netlist-level power analysis
Post-process and script report log files for format conversion, data analysis, and information extraction
Set up, run, debug, and analyze reports of ASIC flows (Synthesis, PD, Power, Timing)
Implement some blocks at RTL and UPF
Document and communicate clearly
MINIMUM QUALIFICATIONS:
10+ years of experience as an ASIC Power Engineer, or CAD Engineer/Physical Design Engineer
Experience with power estimation tools and synthesis, some physical design
Knowledge of power trade-offs in design and back-end implementation
Hands‑on experience in scripting and data analysis
BS in Electrical Engineering, Computer Science, or equivalent experience
PREFERRED QUALIFICATIONS:
Experience with Synopsys tools (DC, ICC, PTPX/PrimePower, VCS, Verdi) and/or Cadence tools (Joules)
Proficiency in Python, Perl (or similar) scripting and data post-processing tools
Skilled in Excel (or Matlab) for model fitting, data visualization, and analysis
Experience in low‑power design, tools, and methodologies including power intent UPF specifications
Silicon power characterization
Power profiling experience at IP/SoC level
BENEFITS SUMMARY:
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate or annual salary only, unless otherwise stated. In addition to base compensation, full‑time roles are eligible for Medical, Dental, Vision, Commuter and 401K benefits with company matching.
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LOCATION: Sunnyvale, CA (Hybrid)
DURATION: 1/8/2026 - 7/7/2026
PAY RANGE: $109-$119/hr.
TOP 3 SKILLS:
Experience with Synopsys (DC, ICC, PTPX/Prime Power, VCS, Verdi) and/or Cadence (Joules)
Should know how to use Python, Perl (or similar) scripting, and data-post-processing tools
Experience in low power design, tools, and methodologies, including power intent UPF specifications, Silicon Power Characterization
COMPANY:
Our client is a Fortune 500 multi-national technology company headquartered in Menlo Park, CA.
DUTIES:
The ASIC Power Engineer will perform power analysis and optimizations in ASIC for AR/VR products. Areas of interest include Machine Learning. Primary languages are Python, Tcl, and SystemVerilog.
RESPONSIBILITIES:
Perform PPA optimization with Fusion Compiler
Conduct RTL and netlist-level power analysis
Post-process and script report log files for format conversion, data analysis, and information extraction
Set up, run, debug, and analyze reports of ASIC flows (Synthesis, PD, Power, Timing)
Implement some blocks at RTL and UPF
Document and communicate clearly
MINIMUM QUALIFICATIONS:
10+ years of experience as an ASIC Power Engineer, or CAD Engineer/Physical Design Engineer
Experience with power estimation tools and synthesis, some physical design
Knowledge of power trade-offs in design and back-end implementation
Hands‑on experience in scripting and data analysis
BS in Electrical Engineering, Computer Science, or equivalent experience
PREFERRED QUALIFICATIONS:
Experience with Synopsys tools (DC, ICC, PTPX/PrimePower, VCS, Verdi) and/or Cadence tools (Joules)
Proficiency in Python, Perl (or similar) scripting and data post-processing tools
Skilled in Excel (or Matlab) for model fitting, data visualization, and analysis
Experience in low‑power design, tools, and methodologies including power intent UPF specifications
Silicon power characterization
Power profiling experience at IP/SoC level
BENEFITS SUMMARY:
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate or annual salary only, unless otherwise stated. In addition to base compensation, full‑time roles are eligible for Medical, Dental, Vision, Commuter and 401K benefits with company matching.
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