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Cadence Design Systems

Emulation Design Lead: High-Speed PHY & AVIP

Cadence Design Systems, San Jose, California, United States, 95199

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A leading technology firm in California is seeking a skilled Design Engineer to join their Palladium Solutions Development team. This role focuses on developing verification environments for high-speed interface circuits. The ideal candidate will have extensive experience in system-level design, proficiency in SystemVerilog, and hands-on experience with emulation platforms like Palladium and Protium. A competitive salary and benefits are offered, including bonus and stock options. #J-18808-Ljbffr