Cadence Design Systems
Senior DDR IP Presales Engineer — Shape Memory Solutions
Cadence Design Systems, San Jose, California, United States, 95199
A leading technology firm in San Jose is seeking a Senior Applications Engineer to support technical presales of DDR IP. This role involves collaborating with Sales and R&D teams, generating simulations, and presenting to customers. The ideal candidate has a BS/MS in Electrical Engineering and experience in Verilog HDL. Competitive salary range from $84,000 to $156,000 is offered along with comprehensive benefits.
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