Senior ASIC Verification Engineer - Performance & SoC

A leading tech company is hiring an ASIC Design Verification Engineer in Sunnyvale, California. This role involves verification closure of design modules for data center applications and requires substantial experience in SystemVerilog/UVM methodologies. Candidates should have a Bachelor’s degree in a related field and at least 8 years of hands-on experience in ASIC development cycles. Competitive compensation, including a salary range of $173,000 to $249,000 plus bonuses and equity, is offered. #J-18808-Ljbffr