Cadence Design Systems, Inc.
Principal Software Engineer - Low Power Verification
Cadence Design Systems, Inc., San Jose, California, United States, 95199
About the Role
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
We are seeking a highly skilled Senior Software Engineer to join our team in developing next-generation low-power verification software for Palladium and Protium emulation systems. This role focuses on enhancing the debuggability and performance of multi-billion-gate UPF (Unified Power Format) designs in modular compilation 2-state and 4-state flows.
Key Responsibilities
Develop and optimize low-power verification software for Palladium and Protium platforms.
Improve UPF design debuggability in IXCOM Modular Compiler and Parallel Partition Compiler (2-state and 4-state flows).
Enhance compiled streaming probes and accelerate waveform generation for large-scale designs.
Collaborate with R&D, Product Engineering (PE), and Application Engineering (AE) teams to deploy UPF solutions across various flows: AVIP + UPF + 2/4-state; UVMA + UPF + 2/4-state; MC + UPF; Dielets + UPF.
Consolidate UPF software across Palladium and Protium platforms.
Support key initiatives such as MC+PPC flow with UPF 4-state; Compilation time optimization for UPF; Full Vision UPF probe integration; SAGE UPF debug with Verisium.
Qualifications
Bachelor’s degree in Computer Science or Electrical Engineering with a minimum of 7 years of relevant experience; Master’s degree with 5+ years of experience; PhD with 1+ year of experience.
Required Skills
Strong proficiency in object-oriented design and C++ programming.
Experience with standard C/C++ libraries and the C++ Standard Template Library (STL).
Proven ability to develop high-performance software for large-scale data processing.
Scripting experience in Perl, Tcl/Tk, and/or Python.
Familiarity with IEEE 1801 standards and UPF implementation.
Experience with Verilog, SystemVerilog, and VHDL.
Salary and Benefits The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
Equal Employment Opportunity Cadence is committed to equal employment opportunity throughout all levels of the organization. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
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We are seeking a highly skilled Senior Software Engineer to join our team in developing next-generation low-power verification software for Palladium and Protium emulation systems. This role focuses on enhancing the debuggability and performance of multi-billion-gate UPF (Unified Power Format) designs in modular compilation 2-state and 4-state flows.
Key Responsibilities
Develop and optimize low-power verification software for Palladium and Protium platforms.
Improve UPF design debuggability in IXCOM Modular Compiler and Parallel Partition Compiler (2-state and 4-state flows).
Enhance compiled streaming probes and accelerate waveform generation for large-scale designs.
Collaborate with R&D, Product Engineering (PE), and Application Engineering (AE) teams to deploy UPF solutions across various flows: AVIP + UPF + 2/4-state; UVMA + UPF + 2/4-state; MC + UPF; Dielets + UPF.
Consolidate UPF software across Palladium and Protium platforms.
Support key initiatives such as MC+PPC flow with UPF 4-state; Compilation time optimization for UPF; Full Vision UPF probe integration; SAGE UPF debug with Verisium.
Qualifications
Bachelor’s degree in Computer Science or Electrical Engineering with a minimum of 7 years of relevant experience; Master’s degree with 5+ years of experience; PhD with 1+ year of experience.
Required Skills
Strong proficiency in object-oriented design and C++ programming.
Experience with standard C/C++ libraries and the C++ Standard Template Library (STL).
Proven ability to develop high-performance software for large-scale data processing.
Scripting experience in Perl, Tcl/Tk, and/or Python.
Familiarity with IEEE 1801 standards and UPF implementation.
Experience with Verilog, SystemVerilog, and VHDL.
Salary and Benefits The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
Equal Employment Opportunity Cadence is committed to equal employment opportunity throughout all levels of the organization. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
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