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Cadence Design Systems

Principal Low-Power Verification Architect (UPF)

Cadence Design Systems, San Jose, California, United States, 95199

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A leading technology firm in San Jose is seeking a Principal Software Engineer to develop low-power verification software for advanced systems. The ideal candidate has strong C++ programming skills and experience in software optimization. You will collaborate with R&D and engineering teams, and require a Bachelor's degree or higher in a relevant field with substantial experience. Competitive compensation, including a salary range of $136,500 to $253,500 and comprehensive benefits, is offered. #J-18808-Ljbffr