Senior FPGA Design Engineer RTL, Vivado & Lab Debug

A leading engineering and R&D services company in California is seeking a skilled designer proficient in RTL design and Vivado Flow. The role entails collaboration with cross-functional teams, developing robust methodologies, and utilizing lab equipment like oscilloscopes and multimeters for troubleshooting. Candidates should have debugging capabilities and familiarity with low-speed protocols. Competitive hybrid work model and benefits are offered. #J-18808-Ljbffr