Senior FPGA Engineer: RTL, Vivado, and Lab Debugging

A leading technology firm is seeking a Senior FPGA Engineer in San Jose, CA. This role involves hands-on RTL design using Vivado, debugging with lab equipment, and collaborating with cross-functional teams to deliver robust FPGA solutions. The ideal candidate will have proficiency in RTL design, experience with oscilloscopes and multimeters, and familiarity with low-speed communication protocols. The company values diversity and encourages all qualified applicants to apply. #J-18808-Ljbffr