Memory PHY RTL Design Engineer - High-Speed IP

A leading technology company is seeking an experienced Design Engineer for RTL and firmware development of high-speed Memory PHYs in Santa Clara, CA. Responsibilities include digital design, PHY architecture development, and collaboration with various engineering teams. Candidates should have a passion for processor architecture and possess strong digital design skills. A Bachelor's or Master's degree in Computer or Electrical Engineering is required, along with experience in Verilog and C/C++. #J-18808-Ljbffr