Cellular SoC STA Engineer: Timing & Sign-off

A leading technology company is seeking a Cellular SoC Static Timing Analysis Engineer to ensure optimal timing performance for Apple's chip designs. The successful candidate will perform static timing analysis, generate constraints, and collaborate with various teams to resolve timing issues. Required qualifications include 10+ years of experience and expertise in ASIC timing tools like Synopsys PrimeTime. #J-18808-Ljbffr