Cellular SoC Timing & Sign-off Engineer

A leading technology company is seeking a Cellular SoC Static Timing Analysis Engineer to ensure precision in timing for chip design. Candidates should have strong knowledge of ASIC timing constraints, proficiency in tools like Synopsys PrimeTime, and excellent communication skills. The base pay range is between $147,400 and $272,100, complemented by stock options and comprehensive benefits including medical coverage and educational reimbursement. #J-18808-Ljbffr