Tesla Motors, Inc.
DFT Verification Engineer, AI Hardware
Tesla Motors, Inc., Palo Alto, California, United States, 94306
What to Expect
Tesla's Silicon Development Team is looking for a Design-for-Test (DFT) Design Verification Engineer to work on custom ASICs. You will drive state of the art pre-silicon DV efforts in verifying the DFT features. We are looking for the best talent to work on state-of-the-art chip designs, where your limit is only your imagination. You will work with a team of highly talented engineers, who are focused on advancing Tesla's AI mission. If you love solving challenging problems, you will fit in very well with our culture.
What You'll Do
Create System Verilog/UVM test benches to verify various DFT features in RTL such as SSN, compressed and uncompressed scan, memory BIST, JTAG, and boundary scan at block and SoC-level
Verify top-level features such as power-on self-test, clock observation, clock stop and scan dump
Verify client-taps and assist in bring up of debug cores like ARM core sight, RISCV debug module, High Speed Phy debug modules
Work with Emulation team in bring up and validation of DFT logic
Run DV regressions & analyze coverage, triage & debug failures
Run gatelevel simulations
Work with the RTL designers on identifying design fixes as needed
Work with test engineers on delivering pre-Si DV testcases for silicon bring up
What You'll Bring
1+ years of DV/DFT DV experience
Degree in Computer Engineering or Electrical Engineering or equivalent experience
Knowledge of testability techniques and features (1149.1, 1149.6, 1687, 1500, Scan, Built-in-Self-Test, Loop-Back etc.) covering digital logic domain, embedded memories, and PHY/IOs and JTAG/1500/1687 networks
Experience in general design verification methodology, regressions, simulation, and debug tools
Experience with CPU/External IP taps/debug cores
Expertise in System-Verilog/UVM
Working knowledge of scripting languages such as TCL, python (or another scripting language such as Perl)
Experience in triaging regressions, debugging, and resolving down to RTL or Testbench issues
Compensation and Benefits Benefits
Aetna PPO and HSA plans > 2 medical plan options with $0 payroll deduction
Family-building, fertility, adoption and surrogacy benefits
Dental (including orthodontic coverage) and vision plans, both have options with a $0 paycheck contribution
Company Paid (Health Savings Account) HSA Contribution when enrolled in the High Deductible Aetna medical plan with HSA
Healthcare and Dependent Care Flexible Spending Accounts (FSA)
401(k) with employer match, Employee Stock Purchase Plans, and other financial benefits
Company paid Basic Life, AD&D, short-term and long-term disability insurance
Employee Assistance Program
Sick and Vacation time (Flex time for salary positions), and Paid Holidays
Back-up childcare and parenting support resources
Voluntary benefits to include: critical illness, hospital indemnity, accident insurance, theft & legal services, and pet insurance
Weight Loss and Tobacco Cessation Programs
Tesla Babies program
Commuter benefits
Employee discounts and perks program
Expected Compensation $120,000 - $228,000/annual salary + cash and stock awards + benefits Pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. The total compensation package for this position may also include other elements dependent on the position offered. Details of participation in these benefit plans will be provided if an employee receives an offer of employment.
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What You'll Do
Create System Verilog/UVM test benches to verify various DFT features in RTL such as SSN, compressed and uncompressed scan, memory BIST, JTAG, and boundary scan at block and SoC-level
Verify top-level features such as power-on self-test, clock observation, clock stop and scan dump
Verify client-taps and assist in bring up of debug cores like ARM core sight, RISCV debug module, High Speed Phy debug modules
Work with Emulation team in bring up and validation of DFT logic
Run DV regressions & analyze coverage, triage & debug failures
Run gatelevel simulations
Work with the RTL designers on identifying design fixes as needed
Work with test engineers on delivering pre-Si DV testcases for silicon bring up
What You'll Bring
1+ years of DV/DFT DV experience
Degree in Computer Engineering or Electrical Engineering or equivalent experience
Knowledge of testability techniques and features (1149.1, 1149.6, 1687, 1500, Scan, Built-in-Self-Test, Loop-Back etc.) covering digital logic domain, embedded memories, and PHY/IOs and JTAG/1500/1687 networks
Experience in general design verification methodology, regressions, simulation, and debug tools
Experience with CPU/External IP taps/debug cores
Expertise in System-Verilog/UVM
Working knowledge of scripting languages such as TCL, python (or another scripting language such as Perl)
Experience in triaging regressions, debugging, and resolving down to RTL or Testbench issues
Compensation and Benefits Benefits
Aetna PPO and HSA plans > 2 medical plan options with $0 payroll deduction
Family-building, fertility, adoption and surrogacy benefits
Dental (including orthodontic coverage) and vision plans, both have options with a $0 paycheck contribution
Company Paid (Health Savings Account) HSA Contribution when enrolled in the High Deductible Aetna medical plan with HSA
Healthcare and Dependent Care Flexible Spending Accounts (FSA)
401(k) with employer match, Employee Stock Purchase Plans, and other financial benefits
Company paid Basic Life, AD&D, short-term and long-term disability insurance
Employee Assistance Program
Sick and Vacation time (Flex time for salary positions), and Paid Holidays
Back-up childcare and parenting support resources
Voluntary benefits to include: critical illness, hospital indemnity, accident insurance, theft & legal services, and pet insurance
Weight Loss and Tobacco Cessation Programs
Tesla Babies program
Commuter benefits
Employee discounts and perks program
Expected Compensation $120,000 - $228,000/annual salary + cash and stock awards + benefits Pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. The total compensation package for this position may also include other elements dependent on the position offered. Details of participation in these benefit plans will be provided if an employee receives an offer of employment.
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