Lead DFT Design Engineer for SoC/ASIC

A leading electronic design automation company in California seeks an experienced SoC/ASIC Digital Design Engineer with a strong focus on Design for Test (DFT) methodologies. The ideal candidate will have substantial expertise in scan chain insertion, compression scan technologies, and automatic test pattern generation (ATPG), along with strong problem-solving skills and the ability to work collaboratively in a cross-functional team environment. This is a fantastic opportunity to contribute to essential technology projects. #J-18808-Ljbffr