Senior Principal DFT Design Engineer for SoC/ASIC Innovation

A leading technology firm in San Jose is seeking an experienced SoC/ASIC Digital Design Engineer focusing on Design for Test (DFT). The ideal candidate will have 5-15 years of experience, specializing in scan chain insertion, memory built-in self-test (MBIST), and Automatic Test Pattern Generation (ATPG). You will work collaboratively and independently to meet design test coverage goals in a fast-paced environment, showcasing strong problem-solving skills and knowledge of Cadence tools. #J-18808-Ljbffr